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xtensa: rename MISC SR definition to avoid name clashes

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There are other special register that cause build warnings and may as
well need renaming as well.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
This commit is contained in:
Max Filippov 2012-09-17 05:44:54 +04:00 committed by Chris Zankel
parent a4c8aa5e5c
commit eb9a63a1e5
1 changed files with 1 additions and 1 deletions
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2
arch/xtensa/include/asm/regs.h
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@ -66,7 +66,7 @@
#define ICOUNTLEVEL 237
#define EXCVADDR 238
#define CCOMPARE 240
#define MISC 244
#define MISC_SR 244
/* Special names for read-only and write-only interrupt registers. */