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power: reset: Add AT91 reset driver
Implement the reset behaviour of the various AT91 SoCS in drivers/power/reset. It used to be (and still is) located in arch/arm/mach-at91, and in order to preserve bisectability is not removed yet, but every board should be converted to use this driver instead. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
This commit is contained in:
Maxime Ripard
parent
6ca4f46005
commit
ecfe64d8c5
@ -14,6 +14,14 @@ config POWER_RESET_AS3722
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help
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This driver supports turning off board via a ams AS3722 power-off.
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config POWER_RESET_AT91_RESET
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bool "Atmel AT91 reset driver"
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depends on MACH_AT91
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default SOC_AT91SAM9 || SOC_SAMA5
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help
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This driver supports restart for Atmel AT91SAM9 and SAMA5
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SoCs
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config POWER_RESET_AXXIA
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bool "LSI Axxia reset driver"
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depends on ARCH_AXXIA
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@ -1,4 +1,5 @@
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obj-$(CONFIG_POWER_RESET_AS3722) += as3722-poweroff.o
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obj-$(CONFIG_POWER_RESET_AT91_RESET) += at91-reset.o
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obj-$(CONFIG_POWER_RESET_AXXIA) += axxia-reset.o
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obj-$(CONFIG_POWER_RESET_GPIO) += gpio-poweroff.o
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obj-$(CONFIG_POWER_RESET_MSM) += msm-poweroff.o
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252
drivers/power/reset/at91-reset.c
Normal file
252
drivers/power/reset/at91-reset.c
Normal file
@ -0,0 +1,252 @@
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/*
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* Atmel AT91 SAM9 SoCs reset code
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*
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* Copyright (C) 2007 Atmel Corporation.
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* Copyright (C) BitBox Ltd 2010
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* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com>
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* Copyright (C) 2014 Free Electrons
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/reboot.h>
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#include <asm/system_misc.h>
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#include <mach/at91sam9_ddrsdr.h>
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#include <mach/at91sam9_sdramc.h>
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#define AT91_RSTC_CR 0x00 /* Reset Controller Control Register */
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#define AT91_RSTC_PROCRST BIT(0) /* Processor Reset */
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#define AT91_RSTC_PERRST BIT(2) /* Peripheral Reset */
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#define AT91_RSTC_EXTRST BIT(3) /* External Reset */
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#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */
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#define AT91_RSTC_SR 0x04 /* Reset Controller Status Register */
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#define AT91_RSTC_URSTS BIT(0) /* User Reset Status */
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#define AT91_RSTC_RSTTYP GENMASK(10, 8) /* Reset Type */
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#define AT91_RSTC_NRSTL BIT(16) /* NRST Pin Level */
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#define AT91_RSTC_SRCMP BIT(17) /* Software Reset Command in Progress */
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#define AT91_RSTC_MR 0x08 /* Reset Controller Mode Register */
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#define AT91_RSTC_URSTEN BIT(0) /* User Reset Enable */
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#define AT91_RSTC_URSTIEN BIT(4) /* User Reset Interrupt Enable */
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#define AT91_RSTC_ERSTL GENMASK(11, 8) /* External Reset Length */
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enum reset_type {
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RESET_TYPE_GENERAL = 0,
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RESET_TYPE_WAKEUP = 1,
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RESET_TYPE_WATCHDOG = 2,
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RESET_TYPE_SOFTWARE = 3,
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RESET_TYPE_USER = 4,
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};
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static void __iomem *at91_ramc_base[2], *at91_rstc_base;
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/*
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* unless the SDRAM is cleanly shutdown before we hit the
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* reset register it can be left driving the data bus and
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* killing the chance of a subsequent boot from NAND
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*/
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static void at91sam9260_restart(enum reboot_mode mode, const char *cmd)
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{
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asm volatile(
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/* Align to cache lines */
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".balign 32\n\t"
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/* Disable SDRAM accesses */
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"str %2, [%0, #" __stringify(AT91_SDRAMC_TR) "]\n\t"
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/* Power down SDRAM */
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"str %3, [%0, #" __stringify(AT91_SDRAMC_LPR) "]\n\t"
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/* Reset CPU */
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"str %4, [%1, #" __stringify(AT91_RSTC_CR) "]\n\t"
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"b .\n\t"
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:
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: "r" (at91_ramc_base[0]),
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"r" (at91_rstc_base),
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"r" (1),
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"r" (AT91_SDRAMC_LPCB_POWER_DOWN),
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"r" (AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST));
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}
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static void at91sam9g45_restart(enum reboot_mode mode, const char *cmd)
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{
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asm volatile(
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/*
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* Test wether we have a second RAM controller to care
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* about.
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*
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* First, test that we can dereference the virtual address.
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*/
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"cmp %1, #0\n\t"
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"beq 1f\n\t"
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/* Then, test that the RAM controller is enabled */
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"ldr r0, [%1]\n\t"
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"cmp r0, #0\n\t"
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/* Align to cache lines */
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".balign 32\n\t"
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/* Disable SDRAM0 accesses */
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"1: str %3, [%0, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t"
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/* Power down SDRAM0 */
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" str %4, [%0, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t"
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/* Disable SDRAM1 accesses */
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" strne %3, [%1, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t"
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/* Power down SDRAM1 */
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" strne %4, [%1, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t"
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/* Reset CPU */
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" str %5, [%2, #" __stringify(AT91_RSTC_CR) "]\n\t"
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" b .\n\t"
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:
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: "r" (at91_ramc_base[0]),
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"r" (at91_ramc_base[1]),
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"r" (at91_rstc_base),
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"r" (1),
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"r" (AT91_DDRSDRC_LPCB_POWER_DOWN),
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"r" (AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST)
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: "r0");
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}
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static void __init at91_reset_status(struct platform_device *pdev)
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{
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u32 reg = readl(at91_rstc_base + AT91_RSTC_SR);
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char *reason;
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switch ((reg & AT91_RSTC_RSTTYP) >> 8) {
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case RESET_TYPE_GENERAL:
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reason = "general reset";
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break;
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case RESET_TYPE_WAKEUP:
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reason = "wakeup";
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break;
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case RESET_TYPE_WATCHDOG:
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reason = "watchdog reset";
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break;
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case RESET_TYPE_SOFTWARE:
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reason = "software reset";
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break;
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case RESET_TYPE_USER:
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reason = "user reset";
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break;
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default:
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reason = "unknown reset";
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break;
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}
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pr_info("AT91: Starting after %s\n", reason);
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}
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static struct of_device_id at91_ramc_of_match[] = {
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{ .compatible = "atmel,at91sam9260-sdramc", },
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{ .compatible = "atmel,at91sam9g45-ddramc", },
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{ .compatible = "atmel,sama5d3-ddramc", },
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{ /* sentinel */ }
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};
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static struct of_device_id at91_reset_of_match[] = {
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{ .compatible = "atmel,at91sam9260-rstc", .data = at91sam9260_restart },
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{ .compatible = "atmel,at91sam9g45-rstc", .data = at91sam9g45_restart },
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{ /* sentinel */ }
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};
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static int at91_reset_of_probe(struct platform_device *pdev)
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{
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const struct of_device_id *match;
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struct device_node *np;
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int idx = 0;
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at91_rstc_base = of_iomap(pdev->dev.of_node, 0);
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if (!at91_rstc_base) {
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dev_err(&pdev->dev, "Could not map reset controller address\n");
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return -ENODEV;
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}
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for_each_matching_node(np, at91_ramc_of_match) {
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at91_ramc_base[idx] = of_iomap(np, 0);
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if (!at91_ramc_base[idx]) {
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dev_err(&pdev->dev, "Could not map ram controller address\n");
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return -ENODEV;
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}
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idx++;
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}
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match = of_match_node(at91_reset_of_match, pdev->dev.of_node);
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arm_pm_restart = match->data;
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return 0;
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}
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static int at91_reset_platform_probe(struct platform_device *pdev)
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{
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const struct platform_device_id *match;
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struct resource *res;
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int idx = 0;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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at91_rstc_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(at91_rstc_base)) {
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dev_err(&pdev->dev, "Could not map reset controller address\n");
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return PTR_ERR(at91_rstc_base);
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}
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for (idx = 0; idx < 2; idx++) {
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res = platform_get_resource(pdev, IORESOURCE_MEM, idx + 1 );
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at91_ramc_base[idx] = devm_ioremap(&pdev->dev, res->start,
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resource_size(res));
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if (IS_ERR(at91_ramc_base[idx])) {
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dev_err(&pdev->dev, "Could not map ram controller address\n");
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return PTR_ERR(at91_ramc_base[idx]);
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}
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}
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match = platform_get_device_id(pdev);
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arm_pm_restart = (void (*)(enum reboot_mode, const char*))
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match->driver_data;
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return 0;
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}
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static int at91_reset_probe(struct platform_device *pdev)
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{
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int ret;
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if (pdev->dev.of_node)
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ret = at91_reset_of_probe(pdev);
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else
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ret = at91_reset_platform_probe(pdev);
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if (ret)
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return ret;
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at91_reset_status(pdev);
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return 0;
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}
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static struct platform_device_id at91_reset_plat_match[] = {
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{ "at91-sam9260-reset", (unsigned long)at91sam9260_restart },
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{ "at91-sam9g45-reset", (unsigned long)at91sam9g45_restart },
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{ /* sentinel */ }
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};
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static struct platform_driver at91_reset_driver = {
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.probe = at91_reset_probe,
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.driver = {
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.name = "at91-reset",
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.of_match_table = at91_reset_of_match,
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},
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.id_table = at91_reset_plat_match,
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};
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module_platform_driver(at91_reset_driver);
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