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Revert "ARCv2: spinlock/rwlock/atomics: Delayed retry of failed SCOND with exponential backoff"
This reverts commit e78fdfef84
.
The issue was fixed in hardware in HS2.1C release and there are no known
external users of affected RTL so revert the whole delayed retry series !
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
parent
819f3602dc
commit
ed6aefed72
@ -389,11 +389,6 @@ config ARC_HAS_LLSC
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default y
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depends on !ARC_CANT_LLSC
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config ARC_STAR_9000923308
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bool "Workaround for llock/scond livelock"
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default n
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depends on ISA_ARCV2 && SMP && ARC_HAS_LLSC
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config ARC_HAS_SWAPE
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bool "Insn: SWAPE (endian-swap)"
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default y
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@ -25,51 +25,17 @@
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#define atomic_set(v, i) WRITE_ONCE(((v)->counter), (i))
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#ifdef CONFIG_ARC_STAR_9000923308
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#define SCOND_FAIL_RETRY_VAR_DEF \
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unsigned int delay = 1, tmp; \
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#define SCOND_FAIL_RETRY_ASM \
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" bz 4f \n" \
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" ; --- scond fail delay --- \n" \
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" mov %[tmp], %[delay] \n" /* tmp = delay */ \
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"2: brne.d %[tmp], 0, 2b \n" /* while (tmp != 0) */ \
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" sub %[tmp], %[tmp], 1 \n" /* tmp-- */ \
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" asl.f %[delay], %[delay], 1 \n" /* delay *= 2 */ \
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" mov.z %[delay], 1 \n" /* handle overflow */ \
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" b 1b \n" /* start over */ \
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"4: ; --- success --- \n" \
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#define SCOND_FAIL_RETRY_VARS \
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,[delay] "+&r" (delay),[tmp] "=&r" (tmp) \
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#else /* !CONFIG_ARC_STAR_9000923308 */
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#define SCOND_FAIL_RETRY_VAR_DEF
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#define SCOND_FAIL_RETRY_ASM \
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" bnz 1b \n" \
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#define SCOND_FAIL_RETRY_VARS
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#endif
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#define ATOMIC_OP(op, c_op, asm_op) \
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static inline void atomic_##op(int i, atomic_t *v) \
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{ \
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unsigned int val; \
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SCOND_FAIL_RETRY_VAR_DEF \
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unsigned int val; \
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\
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__asm__ __volatile__( \
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"1: llock %[val], [%[ctr]] \n" \
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" " #asm_op " %[val], %[val], %[i] \n" \
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" scond %[val], [%[ctr]] \n" \
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" \n" \
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SCOND_FAIL_RETRY_ASM \
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\
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" bnz 1b \n" \
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: [val] "=&r" (val) /* Early clobber to prevent reg reuse */ \
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SCOND_FAIL_RETRY_VARS \
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: [ctr] "r" (&v->counter), /* Not "m": llock only supports reg direct addr mode */ \
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[i] "ir" (i) \
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: "cc"); \
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@ -78,8 +44,7 @@ static inline void atomic_##op(int i, atomic_t *v) \
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#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
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static inline int atomic_##op##_return(int i, atomic_t *v) \
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{ \
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unsigned int val; \
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SCOND_FAIL_RETRY_VAR_DEF \
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unsigned int val; \
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\
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/* \
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* Explicit full memory barrier needed before/after as \
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@ -91,11 +56,8 @@ static inline int atomic_##op##_return(int i, atomic_t *v) \
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"1: llock %[val], [%[ctr]] \n" \
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" " #asm_op " %[val], %[val], %[i] \n" \
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" scond %[val], [%[ctr]] \n" \
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" \n" \
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SCOND_FAIL_RETRY_ASM \
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\
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" bnz 1b \n" \
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: [val] "=&r" (val) \
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SCOND_FAIL_RETRY_VARS \
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: [ctr] "r" (&v->counter), \
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[i] "ir" (i) \
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: "cc"); \
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@ -20,11 +20,6 @@
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#ifdef CONFIG_ARC_HAS_LLSC
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/*
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* A normal LLOCK/SCOND based system, w/o need for livelock workaround
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*/
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#ifndef CONFIG_ARC_STAR_9000923308
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static inline void arch_spin_lock(arch_spinlock_t *lock)
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{
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unsigned int val;
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@ -238,294 +233,6 @@ static inline void arch_write_unlock(arch_rwlock_t *rw)
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smp_mb();
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}
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#else /* CONFIG_ARC_STAR_9000923308 */
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/*
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* HS38x4 could get into a LLOCK/SCOND livelock in case of multiple overlapping
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* coherency transactions in the SCU. The exclusive line state keeps rotating
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* among contenting cores leading to a never ending cycle. So break the cycle
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* by deferring the retry of failed exclusive access (SCOND). The actual delay
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* needed is function of number of contending cores as well as the unrelated
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* coherency traffic from other cores. To keep the code simple, start off with
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* small delay of 1 which would suffice most cases and in case of contention
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* double the delay. Eventually the delay is sufficient such that the coherency
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* pipeline is drained, thus a subsequent exclusive access would succeed.
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*/
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#define SCOND_FAIL_RETRY_VAR_DEF \
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unsigned int delay, tmp; \
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#define SCOND_FAIL_RETRY_ASM \
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" ; --- scond fail delay --- \n" \
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" mov %[tmp], %[delay] \n" /* tmp = delay */ \
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"2: brne.d %[tmp], 0, 2b \n" /* while (tmp != 0) */ \
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" sub %[tmp], %[tmp], 1 \n" /* tmp-- */ \
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" asl.f %[delay], %[delay], 1 \n" /* delay *= 2 */ \
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" mov.z %[delay], 1 \n" /* handle overflow */ \
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" b 1b \n" /* start over */ \
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" \n" \
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"4: ; --- done --- \n" \
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#define SCOND_FAIL_RETRY_VARS \
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,[delay] "=&r" (delay), [tmp] "=&r" (tmp) \
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static inline void arch_spin_lock(arch_spinlock_t *lock)
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{
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unsigned int val;
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SCOND_FAIL_RETRY_VAR_DEF;
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smp_mb();
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__asm__ __volatile__(
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"0: mov %[delay], 1 \n"
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"1: llock %[val], [%[slock]] \n"
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" breq %[val], %[LOCKED], 1b \n" /* spin while LOCKED */
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" scond %[LOCKED], [%[slock]] \n" /* acquire */
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" bz 4f \n" /* done */
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" \n"
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SCOND_FAIL_RETRY_ASM
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: [val] "=&r" (val)
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SCOND_FAIL_RETRY_VARS
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: [slock] "r" (&(lock->slock)),
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[LOCKED] "r" (__ARCH_SPIN_LOCK_LOCKED__)
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: "memory", "cc");
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smp_mb();
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}
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/* 1 - lock taken successfully */
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static inline int arch_spin_trylock(arch_spinlock_t *lock)
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{
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unsigned int val, got_it = 0;
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SCOND_FAIL_RETRY_VAR_DEF;
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smp_mb();
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__asm__ __volatile__(
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"0: mov %[delay], 1 \n"
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"1: llock %[val], [%[slock]] \n"
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" breq %[val], %[LOCKED], 4f \n" /* already LOCKED, just bail */
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" scond %[LOCKED], [%[slock]] \n" /* acquire */
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" bz.d 4f \n"
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" mov.z %[got_it], 1 \n" /* got it */
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" \n"
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SCOND_FAIL_RETRY_ASM
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: [val] "=&r" (val),
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[got_it] "+&r" (got_it)
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SCOND_FAIL_RETRY_VARS
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: [slock] "r" (&(lock->slock)),
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[LOCKED] "r" (__ARCH_SPIN_LOCK_LOCKED__)
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: "memory", "cc");
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smp_mb();
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return got_it;
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}
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static inline void arch_spin_unlock(arch_spinlock_t *lock)
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{
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smp_mb();
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lock->slock = __ARCH_SPIN_LOCK_UNLOCKED__;
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smp_mb();
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}
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/*
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* Read-write spinlocks, allowing multiple readers but only one writer.
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* Unfair locking as Writers could be starved indefinitely by Reader(s)
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*/
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static inline void arch_read_lock(arch_rwlock_t *rw)
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{
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unsigned int val;
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SCOND_FAIL_RETRY_VAR_DEF;
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smp_mb();
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/*
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* zero means writer holds the lock exclusively, deny Reader.
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* Otherwise grant lock to first/subseq reader
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*
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* if (rw->counter > 0) {
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* rw->counter--;
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* ret = 1;
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* }
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*/
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__asm__ __volatile__(
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"0: mov %[delay], 1 \n"
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"1: llock %[val], [%[rwlock]] \n"
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" brls %[val], %[WR_LOCKED], 1b\n" /* <= 0: spin while write locked */
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" sub %[val], %[val], 1 \n" /* reader lock */
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" scond %[val], [%[rwlock]] \n"
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" bz 4f \n" /* done */
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" \n"
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SCOND_FAIL_RETRY_ASM
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: [val] "=&r" (val)
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SCOND_FAIL_RETRY_VARS
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: [rwlock] "r" (&(rw->counter)),
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[WR_LOCKED] "ir" (0)
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: "memory", "cc");
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smp_mb();
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}
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/* 1 - lock taken successfully */
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static inline int arch_read_trylock(arch_rwlock_t *rw)
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{
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unsigned int val, got_it = 0;
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SCOND_FAIL_RETRY_VAR_DEF;
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smp_mb();
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__asm__ __volatile__(
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"0: mov %[delay], 1 \n"
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"1: llock %[val], [%[rwlock]] \n"
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" brls %[val], %[WR_LOCKED], 4f\n" /* <= 0: already write locked, bail */
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" sub %[val], %[val], 1 \n" /* counter-- */
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" scond %[val], [%[rwlock]] \n"
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" bz.d 4f \n"
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" mov.z %[got_it], 1 \n" /* got it */
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" \n"
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SCOND_FAIL_RETRY_ASM
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: [val] "=&r" (val),
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[got_it] "+&r" (got_it)
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SCOND_FAIL_RETRY_VARS
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: [rwlock] "r" (&(rw->counter)),
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[WR_LOCKED] "ir" (0)
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: "memory", "cc");
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smp_mb();
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return got_it;
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}
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static inline void arch_write_lock(arch_rwlock_t *rw)
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{
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unsigned int val;
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SCOND_FAIL_RETRY_VAR_DEF;
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smp_mb();
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/*
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* If reader(s) hold lock (lock < __ARCH_RW_LOCK_UNLOCKED__),
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* deny writer. Otherwise if unlocked grant to writer
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* Hence the claim that Linux rwlocks are unfair to writers.
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* (can be starved for an indefinite time by readers).
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*
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* if (rw->counter == __ARCH_RW_LOCK_UNLOCKED__) {
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* rw->counter = 0;
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* ret = 1;
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* }
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*/
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__asm__ __volatile__(
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"0: mov %[delay], 1 \n"
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"1: llock %[val], [%[rwlock]] \n"
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" brne %[val], %[UNLOCKED], 1b \n" /* while !UNLOCKED spin */
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" mov %[val], %[WR_LOCKED] \n"
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" scond %[val], [%[rwlock]] \n"
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" bz 4f \n"
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" \n"
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SCOND_FAIL_RETRY_ASM
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: [val] "=&r" (val)
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SCOND_FAIL_RETRY_VARS
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: [rwlock] "r" (&(rw->counter)),
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[UNLOCKED] "ir" (__ARCH_RW_LOCK_UNLOCKED__),
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[WR_LOCKED] "ir" (0)
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: "memory", "cc");
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smp_mb();
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}
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/* 1 - lock taken successfully */
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static inline int arch_write_trylock(arch_rwlock_t *rw)
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{
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unsigned int val, got_it = 0;
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SCOND_FAIL_RETRY_VAR_DEF;
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smp_mb();
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__asm__ __volatile__(
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"0: mov %[delay], 1 \n"
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"1: llock %[val], [%[rwlock]] \n"
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" brne %[val], %[UNLOCKED], 4f \n" /* !UNLOCKED, bail */
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" mov %[val], %[WR_LOCKED] \n"
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" scond %[val], [%[rwlock]] \n"
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" bz.d 4f \n"
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" mov.z %[got_it], 1 \n" /* got it */
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" \n"
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SCOND_FAIL_RETRY_ASM
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: [val] "=&r" (val),
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[got_it] "+&r" (got_it)
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SCOND_FAIL_RETRY_VARS
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: [rwlock] "r" (&(rw->counter)),
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[UNLOCKED] "ir" (__ARCH_RW_LOCK_UNLOCKED__),
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[WR_LOCKED] "ir" (0)
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: "memory", "cc");
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smp_mb();
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return got_it;
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}
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static inline void arch_read_unlock(arch_rwlock_t *rw)
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{
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unsigned int val;
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smp_mb();
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/*
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* rw->counter++;
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*/
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__asm__ __volatile__(
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"1: llock %[val], [%[rwlock]] \n"
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" add %[val], %[val], 1 \n"
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" scond %[val], [%[rwlock]] \n"
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" bnz 1b \n"
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" \n"
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: [val] "=&r" (val)
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: [rwlock] "r" (&(rw->counter))
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: "memory", "cc");
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smp_mb();
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}
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static inline void arch_write_unlock(arch_rwlock_t *rw)
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{
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unsigned int val;
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smp_mb();
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/*
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* rw->counter = __ARCH_RW_LOCK_UNLOCKED__;
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*/
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__asm__ __volatile__(
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"1: llock %[val], [%[rwlock]] \n"
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" scond %[UNLOCKED], [%[rwlock]]\n"
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" bnz 1b \n"
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" \n"
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: [val] "=&r" (val)
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: [rwlock] "r" (&(rw->counter)),
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[UNLOCKED] "r" (__ARCH_RW_LOCK_UNLOCKED__)
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: "memory", "cc");
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smp_mb();
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}
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#undef SCOND_FAIL_RETRY_VAR_DEF
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#undef SCOND_FAIL_RETRY_ASM
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#undef SCOND_FAIL_RETRY_VARS
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#endif /* CONFIG_ARC_STAR_9000923308 */
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#else /* !CONFIG_ARC_HAS_LLSC */
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static inline void arch_spin_lock(arch_spinlock_t *lock)
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