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mlxsw: Add PCI bus implementation
Add PCI bus implementation for Mellanox Technologies Switch ASICs. This includes firmware initialization, async queues manipulation and command interface implementation. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Elad Raz <eladr@mellanox.com> Reviewed-by: Scott Feldman <sfeldma@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Jiri Pirko
David S. Miller
parent
93c1edb27f
commit
eda6500a98
@ -9,3 +9,13 @@ config MLXSW_CORE
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To compile this driver as a module, choose M here: the
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module will be called mlxsw_core.
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config MLXSW_PCI
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tristate "PCI bus implementation for Mellanox Technologies Switch ASICs"
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depends on PCI && MLXSW_CORE
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default m
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---help---
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This is PCI bus implementation for Mellanox Technologies Switch ASICs.
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To compile this driver as a module, choose M here: the
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module will be called mlxsw_pci.
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@ -1,2 +1,4 @@
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obj-$(CONFIG_MLXSW_CORE) += mlxsw_core.o
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mlxsw_core-objs := core.o
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obj-$(CONFIG_MLXSW_PCI) += mlxsw_pci.o
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mlxsw_pci-objs := pci.o
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1791
drivers/net/ethernet/mellanox/mlxsw/pci.c
Normal file
1791
drivers/net/ethernet/mellanox/mlxsw/pci.c
Normal file
File diff suppressed because it is too large
Load Diff
220
drivers/net/ethernet/mellanox/mlxsw/pci.h
Normal file
220
drivers/net/ethernet/mellanox/mlxsw/pci.h
Normal file
@ -0,0 +1,220 @@
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/*
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* drivers/net/ethernet/mellanox/mlxsw/pci.h
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* Copyright (c) 2015 Mellanox Technologies. All rights reserved.
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* Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the names of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* Alternatively, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") version 2 as published by the Free
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* Software Foundation.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MLXSW_PCI_H
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#define _MLXSW_PCI_H
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#include <linux/bitops.h>
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#include "item.h"
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#define MLXSW_PCI_BAR0_SIZE (1024 * 1024) /* 1MB */
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#define MLXSW_PCI_PAGE_SIZE 4096
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#define MLXSW_PCI_CIR_BASE 0x71000
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#define MLXSW_PCI_CIR_IN_PARAM_HI MLXSW_PCI_CIR_BASE
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#define MLXSW_PCI_CIR_IN_PARAM_LO (MLXSW_PCI_CIR_BASE + 0x04)
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#define MLXSW_PCI_CIR_IN_MODIFIER (MLXSW_PCI_CIR_BASE + 0x08)
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#define MLXSW_PCI_CIR_OUT_PARAM_HI (MLXSW_PCI_CIR_BASE + 0x0C)
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#define MLXSW_PCI_CIR_OUT_PARAM_LO (MLXSW_PCI_CIR_BASE + 0x10)
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#define MLXSW_PCI_CIR_TOKEN (MLXSW_PCI_CIR_BASE + 0x14)
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#define MLXSW_PCI_CIR_CTRL (MLXSW_PCI_CIR_BASE + 0x18)
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#define MLXSW_PCI_CIR_CTRL_GO_BIT BIT(23)
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#define MLXSW_PCI_CIR_CTRL_EVREQ_BIT BIT(22)
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#define MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT 12
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#define MLXSW_PCI_CIR_CTRL_STATUS_SHIFT 24
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#define MLXSW_PCI_CIR_TIMEOUT_MSECS 1000
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#define MLXSW_PCI_SW_RESET 0xF0010
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#define MLXSW_PCI_SW_RESET_RST_BIT BIT(0)
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#define MLXSW_PCI_SW_RESET_TIMEOUT_MSECS 5000
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#define MLXSW_PCI_DOORBELL_SDQ_OFFSET 0x000
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#define MLXSW_PCI_DOORBELL_RDQ_OFFSET 0x200
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#define MLXSW_PCI_DOORBELL_CQ_OFFSET 0x400
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#define MLXSW_PCI_DOORBELL_EQ_OFFSET 0x600
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#define MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET 0x800
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#define MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET 0xA00
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#define MLXSW_PCI_DOORBELL(offset, type_offset, num) \
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((offset) + (type_offset) + (num) * 4)
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#define MLXSW_PCI_RDQS_COUNT 24
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#define MLXSW_PCI_SDQS_COUNT 24
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#define MLXSW_PCI_CQS_COUNT (MLXSW_PCI_RDQS_COUNT + MLXSW_PCI_SDQS_COUNT)
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#define MLXSW_PCI_EQS_COUNT 2
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#define MLXSW_PCI_EQ_ASYNC_NUM 0
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#define MLXSW_PCI_EQ_COMP_NUM 1
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#define MLXSW_PCI_AQ_PAGES 8
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#define MLXSW_PCI_AQ_SIZE (MLXSW_PCI_PAGE_SIZE * MLXSW_PCI_AQ_PAGES)
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#define MLXSW_PCI_WQE_SIZE 32 /* 32 bytes per element */
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#define MLXSW_PCI_CQE_SIZE 16 /* 16 bytes per element */
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#define MLXSW_PCI_EQE_SIZE 16 /* 16 bytes per element */
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#define MLXSW_PCI_WQE_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_WQE_SIZE)
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#define MLXSW_PCI_CQE_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE_SIZE)
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#define MLXSW_PCI_EQE_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_EQE_SIZE)
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#define MLXSW_PCI_EQE_UPDATE_COUNT 0x80
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#define MLXSW_PCI_WQE_SG_ENTRIES 3
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#define MLXSW_PCI_WQE_TYPE_ETHERNET 0xA
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/* pci_wqe_c
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* If set it indicates that a completion should be reported upon
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* execution of this descriptor.
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*/
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MLXSW_ITEM32(pci, wqe, c, 0x00, 31, 1);
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/* pci_wqe_lp
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* Local Processing, set if packet should be processed by the local
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* switch hardware:
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* For Ethernet EMAD (Direct Route and non Direct Route) -
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* must be set if packet destination is local device
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* For InfiniBand CTL - must be set if packet destination is local device
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* Otherwise it must be clear
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* Local Process packets must not exceed the size of 2K (including payload
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* and headers).
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*/
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MLXSW_ITEM32(pci, wqe, lp, 0x00, 30, 1);
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/* pci_wqe_type
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* Packet type.
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*/
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MLXSW_ITEM32(pci, wqe, type, 0x00, 23, 4);
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/* pci_wqe_byte_count
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* Size of i-th scatter/gather entry, 0 if entry is unused.
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*/
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MLXSW_ITEM16_INDEXED(pci, wqe, byte_count, 0x02, 0, 14, 0x02, 0x00, false);
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/* pci_wqe_address
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* Physical address of i-th scatter/gather entry.
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* Gather Entries must be 2Byte aligned.
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*/
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MLXSW_ITEM64_INDEXED(pci, wqe, address, 0x08, 0, 64, 0x8, 0x0, false);
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/* pci_cqe_lag
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* Packet arrives from a port which is a LAG
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*/
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MLXSW_ITEM32(pci, cqe, lag, 0x00, 23, 1);
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/* pci_cqe_system_port
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* When lag=0: System port on which the packet was received
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* When lag=1:
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* bits [15:4] LAG ID on which the packet was received
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* bits [3:0] sub_port on which the packet was received
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*/
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MLXSW_ITEM32(pci, cqe, system_port, 0x00, 0, 16);
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/* pci_cqe_wqe_counter
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* WQE count of the WQEs completed on the associated dqn
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*/
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MLXSW_ITEM32(pci, cqe, wqe_counter, 0x04, 16, 16);
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/* pci_cqe_byte_count
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* Byte count of received packets including additional two
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* Reserved Bytes that are append to the end of the frame.
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* Reserved for Send CQE.
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*/
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MLXSW_ITEM32(pci, cqe, byte_count, 0x04, 0, 14);
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/* pci_cqe_trap_id
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* Trap ID that captured the packet.
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*/
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MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 8);
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/* pci_cqe_e
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* CQE with Error.
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*/
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MLXSW_ITEM32(pci, cqe, e, 0x0C, 7, 1);
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/* pci_cqe_sr
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* 1 - Send Queue
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* 0 - Receive Queue
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*/
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MLXSW_ITEM32(pci, cqe, sr, 0x0C, 6, 1);
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/* pci_cqe_dqn
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* Descriptor Queue (DQ) Number.
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*/
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MLXSW_ITEM32(pci, cqe, dqn, 0x0C, 1, 5);
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/* pci_cqe_owner
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* Ownership bit.
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*/
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MLXSW_ITEM32(pci, cqe, owner, 0x0C, 0, 1);
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/* pci_eqe_event_type
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* Event type.
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*/
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MLXSW_ITEM32(pci, eqe, event_type, 0x0C, 24, 8);
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#define MLXSW_PCI_EQE_EVENT_TYPE_COMP 0x00
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#define MLXSW_PCI_EQE_EVENT_TYPE_CMD 0x0A
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/* pci_eqe_event_sub_type
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* Event type.
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*/
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MLXSW_ITEM32(pci, eqe, event_sub_type, 0x0C, 16, 8);
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/* pci_eqe_cqn
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* Completion Queue that triggeret this EQE.
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*/
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MLXSW_ITEM32(pci, eqe, cqn, 0x0C, 8, 7);
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/* pci_eqe_owner
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* Ownership bit.
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*/
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MLXSW_ITEM32(pci, eqe, owner, 0x0C, 0, 1);
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/* pci_eqe_cmd_token
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* Command completion event - token
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*/
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MLXSW_ITEM32(pci, eqe, cmd_token, 0x08, 16, 16);
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/* pci_eqe_cmd_status
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* Command completion event - status
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*/
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MLXSW_ITEM32(pci, eqe, cmd_status, 0x08, 0, 8);
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/* pci_eqe_cmd_out_param_h
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* Command completion event - output parameter - higher part
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*/
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MLXSW_ITEM32(pci, eqe, cmd_out_param_h, 0x0C, 0, 32);
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/* pci_eqe_cmd_out_param_l
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* Command completion event - output parameter - lower part
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*/
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MLXSW_ITEM32(pci, eqe, cmd_out_param_l, 0x10, 0, 32);
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#endif
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