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KVM: PPC: Book3S HV: Translate kvmhv_commence_exit to C
This replaces the assembler code for kvmhv_commence_exit() with C code in book3s_hv_builtin.c. It also moves the IPI sending code that was in book3s_hv_rm_xics.c into a new kvmhv_rm_send_ipi() function so it can be used by kvmhv_commence_exit() as well as icp_rm_set_vcpu_irq(). Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Paul Mackerras
Alexander Graf
parent
6af27c847a
commit
eddb60fb14
@ -438,6 +438,8 @@ static inline struct kvm_memslots *kvm_memslots_raw(struct kvm *kvm)
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extern void kvmppc_mmu_debugfs_init(struct kvm *kvm);
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extern void kvmhv_rm_send_ipi(int cpu);
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#endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
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#endif /* __ASM_KVM_BOOK3S_64_H__ */
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@ -22,6 +22,7 @@
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#include <asm/kvm_ppc.h>
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#include <asm/kvm_book3s.h>
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#include <asm/archrandom.h>
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#include <asm/xics.h>
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#define KVM_CMA_CHUNK_ORDER 18
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@ -184,3 +185,65 @@ long kvmppc_h_random(struct kvm_vcpu *vcpu)
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return H_HARDWARE;
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}
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static inline void rm_writeb(unsigned long paddr, u8 val)
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{
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__asm__ __volatile__("stbcix %0,0,%1"
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: : "r" (val), "r" (paddr) : "memory");
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}
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/*
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* Send an interrupt to another CPU.
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* This can only be called in real mode.
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* The caller needs to include any barrier needed to order writes
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* to memory vs. the IPI/message.
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*/
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void kvmhv_rm_send_ipi(int cpu)
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{
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unsigned long xics_phys;
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/* Poke the target */
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xics_phys = paca[cpu].kvm_hstate.xics_phys;
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rm_writeb(xics_phys + XICS_MFRR, IPI_PRIORITY);
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}
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/*
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* The following functions are called from the assembly code
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* in book3s_hv_rmhandlers.S.
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*/
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static void kvmhv_interrupt_vcore(struct kvmppc_vcore *vc, int active)
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{
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int cpu = vc->pcpu;
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/* Order setting of exit map vs. msgsnd/IPI */
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smp_mb();
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for (; active; active >>= 1, ++cpu)
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if (active & 1)
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kvmhv_rm_send_ipi(cpu);
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}
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void kvmhv_commence_exit(int trap)
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{
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struct kvmppc_vcore *vc = local_paca->kvm_hstate.kvm_vcore;
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int ptid = local_paca->kvm_hstate.ptid;
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int me, ee;
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/* Set our bit in the threads-exiting-guest map in the 0xff00
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bits of vcore->entry_exit_map */
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me = 0x100 << ptid;
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do {
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ee = vc->entry_exit_map;
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} while (cmpxchg(&vc->entry_exit_map, ee, ee | me) != ee);
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/* Are we the first here? */
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if ((ee >> 8) != 0)
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return;
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/*
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* Trigger the other threads in this vcore to exit the guest.
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* If this is a hypervisor decrementer interrupt then they
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* will be already on their way out of the guest.
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*/
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if (trap != BOOK3S_INTERRUPT_HV_DECREMENTER)
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kvmhv_interrupt_vcore(vc, ee & ~(1 << ptid));
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}
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@ -26,12 +26,6 @@
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static void icp_rm_deliver_irq(struct kvmppc_xics *xics, struct kvmppc_icp *icp,
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u32 new_irq);
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static inline void rm_writeb(unsigned long paddr, u8 val)
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{
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__asm__ __volatile__("sync; stbcix %0,0,%1"
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: : "r" (val), "r" (paddr) : "memory");
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}
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/* -- ICS routines -- */
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static void ics_rm_check_resend(struct kvmppc_xics *xics,
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struct kvmppc_ics *ics, struct kvmppc_icp *icp)
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@ -60,7 +54,6 @@ static void icp_rm_set_vcpu_irq(struct kvm_vcpu *vcpu,
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struct kvm_vcpu *this_vcpu)
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{
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struct kvmppc_icp *this_icp = this_vcpu->arch.icp;
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unsigned long xics_phys;
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int cpu;
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/* Mark the target VCPU as having an interrupt pending */
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@ -83,9 +76,8 @@ static void icp_rm_set_vcpu_irq(struct kvm_vcpu *vcpu,
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/* In SMT cpu will always point to thread 0, we adjust it */
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cpu += vcpu->arch.ptid;
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/* Not too hard, then poke the target */
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xics_phys = paca[cpu].kvm_hstate.xics_phys;
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rm_writeb(xics_phys + XICS_MFRR, IPI_PRIORITY);
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smp_mb();
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kvmhv_rm_send_ipi(cpu);
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}
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static void icp_rm_clr_vcpu_irq(struct kvm_vcpu *vcpu)
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@ -264,7 +264,11 @@ kvm_novcpu_exit:
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addi r3, r4, VCPU_TB_RMEXIT
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bl kvmhv_accumulate_time
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#endif
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13: bl kvmhv_commence_exit
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13: mr r3, r12
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stw r12, 112-4(r1)
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bl kvmhv_commence_exit
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nop
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lwz r12, 112-4(r1)
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b kvmhv_switch_to_host
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/*
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@ -1161,6 +1165,9 @@ mc_cont:
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/* Increment exit count, poke other threads to exit */
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bl kvmhv_commence_exit
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nop
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ld r9, HSTATE_KVM_VCPU(r13)
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lwz r12, VCPU_TRAP(r9)
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/* Save guest CTRL register, set runlatch to 1 */
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mfspr r6,SPRN_CTRLF
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@ -1614,63 +1621,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
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mtlr r0
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blr
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kvmhv_commence_exit: /* r12 = trap, r13 = paca, doesn't trash r9 */
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mflr r0
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std r0, PPC_LR_STKOFF(r1)
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stdu r1, -PPC_MIN_STKFRM(r1)
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/* Set our bit in the threads-exiting-guest map in the 0xff00
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bits of vcore->entry_exit_map */
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ld r5, HSTATE_KVM_VCORE(r13)
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lbz r4, HSTATE_PTID(r13)
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li r7, 0x100
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sld r7, r7, r4
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addi r6, r5, VCORE_ENTRY_EXIT
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41: lwarx r3, 0, r6
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or r0, r3, r7
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stwcx. r0, 0, r6
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bne 41b
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isync /* order stwcx. vs. reading napping_threads */
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/*
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* At this point we have an interrupt that we have to pass
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* up to the kernel or qemu; we can't handle it in real mode.
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* Thus we have to do a partition switch, so we have to
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* collect the other threads, if we are the first thread
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* to take an interrupt. To do this, we send a message or
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* IPI to all the threads that have their bit set in the entry
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* map in vcore->entry_exit_map (other than ourselves).
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* However, we don't need to bother if this is an HDEC
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* interrupt, since the other threads will already be on their
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* way here in that case.
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*/
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cmpwi r3,0x100 /* Are we the first here? */
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bge 43f
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cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
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beq 43f
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srwi r0,r7,8
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andc. r3,r3,r0 /* no sense IPI'ing ourselves */
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beq 43f
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/* Order entry/exit update vs. IPIs */
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sync
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mulli r4,r4,PACA_SIZE /* get paca for thread 0 */
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subf r6,r4,r13
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42: andi. r0,r3,1
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beq 44f
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ld r8,HSTATE_XICS_PHYS(r6) /* get thread's XICS reg addr */
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li r0,IPI_PRIORITY
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li r7,XICS_MFRR
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stbcix r0,r7,r8 /* trigger the IPI */
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44: srdi. r3,r3,1
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addi r6,r6,PACA_SIZE
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bne 42b
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43: ld r0, PPC_MIN_STKFRM+PPC_LR_STKOFF(r1)
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addi r1, r1, PPC_MIN_STKFRM
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mtlr r0
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blr
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/*
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* Check whether an HDSI is an HPTE not found fault or something else.
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* If it is an HPTE not found fault that is due to the guest accessing
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