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ASoC: Intel: Fix naming of HMDC register macros.
HMDC is the correct naming for this register. Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com> Signed-off-by: Jie Yang <yang.jie@intel.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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@ -52,7 +52,7 @@
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#define SST_CLKCTL 0x78
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#define SST_CLKCTL 0x78
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#define SST_CSR2 0x80
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#define SST_CSR2 0x80
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#define SST_LTRC 0xE0
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#define SST_LTRC 0xE0
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#define SST_HDMC 0xE8
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#define SST_HMDC 0xE8
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#define SST_SHIM_BEGIN SST_CSR
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#define SST_SHIM_BEGIN SST_CSR
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#define SST_SHIM_END SST_HDMC
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#define SST_SHIM_END SST_HDMC
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@ -122,9 +122,9 @@
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/* LTRC */
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/* LTRC */
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#define SST_LTRC_VAL(x) (x << 0)
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#define SST_LTRC_VAL(x) (x << 0)
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/* HDMC */
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/* HMDC */
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#define SST_HDMC_HDDA0(x) (x << 0)
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#define SST_HMDC_HDDA0(x) (x << 0)
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#define SST_HDMC_HDDA1(x) (x << 7)
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#define SST_HMDC_HDDA1(x) (x << 7)
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/* SST Vendor Defined Registers and bits */
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/* SST Vendor Defined Registers and bits */
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@ -269,9 +269,9 @@ static void hsw_boot(struct sst_dsp *sst)
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SST_CSR2_SDFD_SSP1);
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SST_CSR2_SDFD_SSP1);
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/* enable DMA engine 0,1 all channels to access host memory */
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/* enable DMA engine 0,1 all channels to access host memory */
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sst_dsp_shim_update_bits_unlocked(sst, SST_HDMC,
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sst_dsp_shim_update_bits_unlocked(sst, SST_HMDC,
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SST_HDMC_HDDA1(0xff) | SST_HDMC_HDDA0(0xff),
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SST_HMDC_HDDA1(0xff) | SST_HMDC_HDDA0(0xff),
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SST_HDMC_HDDA1(0xff) | SST_HDMC_HDDA0(0xff));
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SST_HMDC_HDDA1(0xff) | SST_HMDC_HDDA0(0xff));
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/* disable all clock gating */
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/* disable all clock gating */
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writel(0x0, sst->addr.pci_cfg + SST_VDRTCTL2);
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writel(0x0, sst->addr.pci_cfg + SST_VDRTCTL2);
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