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ASoC: TWL4030: Optimize the power up sequence
Since the reg cache now contains the chip default values for all registers (REG_OPTION is reset to it's default within this patch), there is no longer need to rewrite _all_ registers. Initialize only few selected registers. According to the latest information, the offset cancellation need to be done only once, when the codec is powered on, so there is no need for the power up wrapper. Move all chip initialization code under chip_init, and do it when the codec is initialized. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
This commit is contained in:
Peter Ujfalusi
Liam Girdwood
parent
979bb1f4b8
commit
ee4ccac7ce
@ -43,7 +43,7 @@
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static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
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0x00, /* this register not used */
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0x00, /* REG_CODEC_MODE (0x1) */
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0xc3, /* REG_OPTION (0x2) */
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0x00, /* REG_OPTION (0x2) */
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0x00, /* REG_UNKNOWN (0x3) */
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0x00, /* REG_MICBIAS_CTL (0x4) */
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0x00, /* REG_ANAMICL (0x5) */
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@ -243,19 +243,67 @@ static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
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udelay(10);
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}
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static void twl4030_init_chip(struct snd_soc_codec *codec)
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static void twl4030_init_chip(struct platform_device *pdev)
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{
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u8 *cache = codec->reg_cache;
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int i;
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struct snd_soc_device *socdev = platform_get_drvdata(pdev);
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struct twl4030_setup_data *setup = socdev->codec_data;
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struct snd_soc_codec *codec = socdev->card->codec;
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struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
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u8 reg, byte;
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int i = 0;
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/* Refresh APLL_CTL register from HW */
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twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
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TWL4030_REG_APLL_CTL);
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twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, byte);
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/* anti-pop when changing analog gain */
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reg = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
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twl4030_write(codec, TWL4030_REG_MISC_SET_1,
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reg | TWL4030_SMOOTH_ANAVOL_EN);
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twl4030_write(codec, TWL4030_REG_OPTION,
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TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |
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TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);
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/* Machine dependent setup */
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if (!setup)
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return;
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/* Configuration for headset ramp delay from setup data */
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if (setup->sysclk != twl4030->sysclk)
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dev_warn(codec->dev,
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"Mismatch in APLL mclk: %u (configured: %u)\n",
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setup->sysclk, twl4030->sysclk);
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reg = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
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reg &= ~TWL4030_RAMP_DELAY;
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reg |= (setup->ramp_delay_value << 2);
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twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, reg);
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/* initiate offset cancellation */
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twl4030_codec_enable(codec, 1);
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reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
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reg &= ~TWL4030_OFFSET_CNCL_SEL;
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reg |= setup->offset_cncl_path;
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twl4030_write(codec, TWL4030_REG_ANAMICL,
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reg | TWL4030_CNCL_OFFSET_START);
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/* wait for offset cancellation to complete */
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do {
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/* this takes a little while, so don't slam i2c */
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udelay(2000);
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twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
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TWL4030_REG_ANAMICL);
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} while ((i++ < 100) &&
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((byte & TWL4030_CNCL_OFFSET_START) ==
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TWL4030_CNCL_OFFSET_START));
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/* Make sure that the reg_cache has the same value as the HW */
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twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
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/* clear CODECPDZ prior to setting register defaults */
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twl4030_codec_enable(codec, 0);
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/* set all audio section registers to reasonable defaults */
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for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
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if (i != TWL4030_REG_APLL_CTL)
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twl4030_write(codec, i, cache[i]);
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}
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static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
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@ -279,50 +327,6 @@ static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
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twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
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}
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static void twl4030_power_up(struct snd_soc_codec *codec)
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{
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struct snd_soc_device *socdev = codec->socdev;
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struct twl4030_setup_data *setup = socdev->codec_data;
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struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
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u8 anamicl, regmisc1, byte;
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int i = 0;
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if (twl4030->codec_powered)
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return;
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/* set CODECPDZ to turn on codec */
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twl4030_codec_enable(codec, 1);
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/* initiate offset cancellation */
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anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
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anamicl &= ~TWL4030_OFFSET_CNCL_SEL;
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anamicl |= setup->offset_cncl_path;
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twl4030_write(codec, TWL4030_REG_ANAMICL,
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anamicl | TWL4030_CNCL_OFFSET_START);
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/* wait for offset cancellation to complete */
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do {
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/* this takes a little while, so don't slam i2c */
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udelay(2000);
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twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
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TWL4030_REG_ANAMICL);
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} while ((i++ < 100) &&
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((byte & TWL4030_CNCL_OFFSET_START) ==
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TWL4030_CNCL_OFFSET_START));
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/* Make sure that the reg_cache has the same value as the HW */
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twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
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/* anti-pop when changing analog gain */
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regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
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twl4030_write(codec, TWL4030_REG_MISC_SET_1,
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regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
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/* toggle CODECPDZ as per TRM */
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twl4030_codec_enable(codec, 0);
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twl4030_codec_enable(codec, 1);
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}
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/* Earpiece */
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static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
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SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
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@ -1599,7 +1603,7 @@ static int twl4030_set_bias_level(struct snd_soc_codec *codec,
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break;
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case SND_SOC_BIAS_STANDBY:
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if (codec->bias_level == SND_SOC_BIAS_OFF)
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twl4030_power_up(codec);
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twl4030_codec_enable(codec, 1);
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break;
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case SND_SOC_BIAS_OFF:
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twl4030_codec_enable(codec, 0);
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@ -2196,31 +2200,16 @@ static struct snd_soc_codec *twl4030_codec;
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static int twl4030_soc_probe(struct platform_device *pdev)
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{
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struct snd_soc_device *socdev = platform_get_drvdata(pdev);
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struct twl4030_setup_data *setup = socdev->codec_data;
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struct snd_soc_codec *codec;
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struct twl4030_priv *twl4030;
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int ret;
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BUG_ON(!twl4030_codec);
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codec = twl4030_codec;
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twl4030 = snd_soc_codec_get_drvdata(codec);
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socdev->card->codec = codec;
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/* Configuration for headset ramp delay from setup data */
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if (setup) {
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unsigned char hs_pop;
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if (setup->sysclk != twl4030->sysclk)
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dev_warn(&pdev->dev,
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"Mismatch in APLL mclk: %u (configured: %u)\n",
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setup->sysclk, twl4030->sysclk);
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hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
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hs_pop &= ~TWL4030_RAMP_DELAY;
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hs_pop |= (setup->ramp_delay_value << 2);
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twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
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}
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twl4030_init_chip(pdev);
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twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
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/* register pcms */
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ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
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@ -2296,9 +2285,7 @@ static int __devinit twl4030_codec_probe(struct platform_device *pdev)
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/* Set the defaults, and power up the codec */
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twl4030->sysclk = twl4030_codec_get_mclk() / 1000;
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twl4030_init_chip(codec);
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codec->bias_level = SND_SOC_BIAS_OFF;
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twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
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ret = snd_soc_register_codec(codec);
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if (ret != 0) {
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