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ARM: S3C24XX: move s3c2416 irq init to common irq code
This is needed to further clean up the irq init. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Heiko Stuebner
Kukjin Kim
parent
b4a343e5b3
commit
ef602eb53c
@ -28,7 +28,7 @@ obj-$(CONFIG_S3C2412_DMA) += dma-s3c2412.o
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obj-$(CONFIG_S3C2412_PM) += pm-s3c2412.o
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obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep-s3c2412.o
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obj-$(CONFIG_CPU_S3C2416) += s3c2416.o irq-s3c2416.o clock-s3c2416.o
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obj-$(CONFIG_CPU_S3C2416) += s3c2416.o clock-s3c2416.o
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obj-$(CONFIG_S3C2416_PM) += pm-s3c2416.o
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obj-$(CONFIG_CPU_S3C2440) += s3c2440.o irq-s3c2440.o clock-s3c2440.o
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@ -99,3 +99,26 @@ struct syscore_ops s3c24xx_irq_syscore_ops = {
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.suspend = s3c24xx_irq_suspend,
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.resume = s3c24xx_irq_resume,
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};
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#ifdef CONFIG_CPU_S3C2416
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static struct sleep_save s3c2416_irq_save[] = {
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SAVE_ITEM(S3C2416_INTMSK2),
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};
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static int s3c2416_irq_suspend(void)
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{
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s3c_pm_do_save(s3c2416_irq_save, ARRAY_SIZE(s3c2416_irq_save));
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return 0;
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}
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static void s3c2416_irq_resume(void)
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{
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s3c_pm_do_restore(s3c2416_irq_save, ARRAY_SIZE(s3c2416_irq_save));
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}
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struct syscore_ops s3c2416_irq_syscore_ops = {
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.suspend = s3c2416_irq_suspend,
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.resume = s3c2416_irq_resume,
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};
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#endif
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@ -1,348 +0,0 @@
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/* linux/arch/arm/mach-s3c2416/irq.c
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*
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* Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
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* as part of OpenInkpot project
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* Copyright (c) 2009 Promwad Innovation Company
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* Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/syscore_ops.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include <mach/regs-irq.h>
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#include <mach/regs-gpio.h>
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#include <plat/cpu.h>
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#include <plat/pm.h>
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#include <plat/irq.h>
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#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
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static inline void s3c2416_irq_demux(unsigned int irq, unsigned int len)
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{
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unsigned int subsrc, submsk;
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unsigned int end;
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/* read the current pending interrupts, and the mask
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* for what it is available */
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subsrc = __raw_readl(S3C2410_SUBSRCPND);
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submsk = __raw_readl(S3C2410_INTSUBMSK);
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subsrc &= ~submsk;
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subsrc >>= (irq - S3C2410_IRQSUB(0));
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subsrc &= (1 << len)-1;
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end = len + irq;
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for (; irq < end && subsrc; irq++) {
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if (subsrc & 1)
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generic_handle_irq(irq);
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subsrc >>= 1;
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}
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}
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/* WDT/AC97 sub interrupts */
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static void s3c2416_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc)
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{
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s3c2416_irq_demux(IRQ_S3C2443_WDT, 4);
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}
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#define INTMSK_WDTAC97 (1UL << (IRQ_WDT - IRQ_EINT0))
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#define SUBMSK_WDTAC97 INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97)
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static void s3c2416_irq_wdtac97_mask(struct irq_data *data)
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{
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s3c_irqsub_mask(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
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}
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static void s3c2416_irq_wdtac97_unmask(struct irq_data *data)
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{
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s3c_irqsub_unmask(data->irq, INTMSK_WDTAC97);
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}
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static void s3c2416_irq_wdtac97_ack(struct irq_data *data)
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{
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s3c_irqsub_maskack(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
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}
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static struct irq_chip s3c2416_irq_wdtac97 = {
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.irq_mask = s3c2416_irq_wdtac97_mask,
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.irq_unmask = s3c2416_irq_wdtac97_unmask,
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.irq_ack = s3c2416_irq_wdtac97_ack,
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};
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/* LCD sub interrupts */
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static void s3c2416_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
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{
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s3c2416_irq_demux(IRQ_S3C2443_LCD1, 4);
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}
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#define INTMSK_LCD (1UL << (IRQ_LCD - IRQ_EINT0))
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#define SUBMSK_LCD INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4)
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static void s3c2416_irq_lcd_mask(struct irq_data *data)
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{
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s3c_irqsub_mask(data->irq, INTMSK_LCD, SUBMSK_LCD);
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}
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static void s3c2416_irq_lcd_unmask(struct irq_data *data)
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{
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s3c_irqsub_unmask(data->irq, INTMSK_LCD);
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}
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static void s3c2416_irq_lcd_ack(struct irq_data *data)
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{
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s3c_irqsub_maskack(data->irq, INTMSK_LCD, SUBMSK_LCD);
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}
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static struct irq_chip s3c2416_irq_lcd = {
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.irq_mask = s3c2416_irq_lcd_mask,
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.irq_unmask = s3c2416_irq_lcd_unmask,
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.irq_ack = s3c2416_irq_lcd_ack,
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};
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/* DMA sub interrupts */
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static void s3c2416_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
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{
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s3c2416_irq_demux(IRQ_S3C2443_DMA0, 6);
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}
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#define INTMSK_DMA (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0))
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#define SUBMSK_DMA INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5)
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static void s3c2416_irq_dma_mask(struct irq_data *data)
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{
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s3c_irqsub_mask(data->irq, INTMSK_DMA, SUBMSK_DMA);
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}
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static void s3c2416_irq_dma_unmask(struct irq_data *data)
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{
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s3c_irqsub_unmask(data->irq, INTMSK_DMA);
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}
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static void s3c2416_irq_dma_ack(struct irq_data *data)
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{
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s3c_irqsub_maskack(data->irq, INTMSK_DMA, SUBMSK_DMA);
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}
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static struct irq_chip s3c2416_irq_dma = {
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.irq_mask = s3c2416_irq_dma_mask,
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.irq_unmask = s3c2416_irq_dma_unmask,
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.irq_ack = s3c2416_irq_dma_ack,
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};
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/* UART3 sub interrupts */
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static void s3c2416_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
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{
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s3c2416_irq_demux(IRQ_S3C2443_RX3, 3);
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}
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#define INTMSK_UART3 (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0))
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#define SUBMSK_UART3 (0x7 << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0)))
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static void s3c2416_irq_uart3_mask(struct irq_data *data)
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{
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s3c_irqsub_mask(data->irq, INTMSK_UART3, SUBMSK_UART3);
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}
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static void s3c2416_irq_uart3_unmask(struct irq_data *data)
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{
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s3c_irqsub_unmask(data->irq, INTMSK_UART3);
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}
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static void s3c2416_irq_uart3_ack(struct irq_data *data)
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{
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s3c_irqsub_maskack(data->irq, INTMSK_UART3, SUBMSK_UART3);
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}
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static struct irq_chip s3c2416_irq_uart3 = {
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.irq_mask = s3c2416_irq_uart3_mask,
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.irq_unmask = s3c2416_irq_uart3_unmask,
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.irq_ack = s3c2416_irq_uart3_ack,
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};
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/* second interrupt register */
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static inline void s3c2416_irq_ack_second(struct irq_data *data)
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{
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unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D);
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__raw_writel(bitval, S3C2416_SRCPND2);
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__raw_writel(bitval, S3C2416_INTPND2);
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}
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static void s3c2416_irq_mask_second(struct irq_data *data)
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{
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unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D);
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unsigned long mask;
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mask = __raw_readl(S3C2416_INTMSK2);
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mask |= bitval;
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__raw_writel(mask, S3C2416_INTMSK2);
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}
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static void s3c2416_irq_unmask_second(struct irq_data *data)
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{
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unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D);
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unsigned long mask;
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mask = __raw_readl(S3C2416_INTMSK2);
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mask &= ~bitval;
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__raw_writel(mask, S3C2416_INTMSK2);
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}
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struct irq_chip s3c2416_irq_second = {
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.irq_ack = s3c2416_irq_ack_second,
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.irq_mask = s3c2416_irq_mask_second,
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.irq_unmask = s3c2416_irq_unmask_second,
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};
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/* IRQ initialisation code */
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static int s3c2416_add_sub(unsigned int base,
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void (*demux)(unsigned int,
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struct irq_desc *),
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struct irq_chip *chip,
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unsigned int start, unsigned int end)
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{
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unsigned int irqno;
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irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq);
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irq_set_chained_handler(base, demux);
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for (irqno = start; irqno <= end; irqno++) {
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irq_set_chip_and_handler(irqno, chip, handle_level_irq);
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set_irq_flags(irqno, IRQF_VALID);
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}
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return 0;
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}
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static void s3c2416_irq_add_second(void)
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{
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unsigned long pend;
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unsigned long last;
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int irqno;
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int i;
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/* first, clear all interrupts pending... */
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last = 0;
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for (i = 0; i < 4; i++) {
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pend = __raw_readl(S3C2416_INTPND2);
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if (pend == 0 || pend == last)
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break;
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__raw_writel(pend, S3C2416_SRCPND2);
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__raw_writel(pend, S3C2416_INTPND2);
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printk(KERN_INFO "irq: clearing pending status %08x\n",
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(int)pend);
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last = pend;
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}
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for (irqno = IRQ_S3C2416_2D; irqno <= IRQ_S3C2416_I2S1; irqno++) {
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switch (irqno) {
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case IRQ_S3C2416_RESERVED2:
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case IRQ_S3C2416_RESERVED3:
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/* no IRQ here */
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break;
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default:
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irq_set_chip_and_handler(irqno, &s3c2416_irq_second,
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handle_edge_irq);
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set_irq_flags(irqno, IRQF_VALID);
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}
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}
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}
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static int s3c2416_irq_add(struct device *dev,
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struct subsys_interface *sif)
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{
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printk(KERN_INFO "S3C2416: IRQ Support\n");
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s3c2416_add_sub(IRQ_LCD, s3c2416_irq_demux_lcd, &s3c2416_irq_lcd,
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IRQ_S3C2443_LCD2, IRQ_S3C2443_LCD4);
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s3c2416_add_sub(IRQ_S3C2443_DMA, s3c2416_irq_demux_dma,
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&s3c2416_irq_dma, IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5);
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s3c2416_add_sub(IRQ_S3C2443_UART3, s3c2416_irq_demux_uart3,
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&s3c2416_irq_uart3,
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IRQ_S3C2443_RX3, IRQ_S3C2443_ERR3);
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s3c2416_add_sub(IRQ_WDT, s3c2416_irq_demux_wdtac97,
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&s3c2416_irq_wdtac97,
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IRQ_S3C2443_WDT, IRQ_S3C2443_AC97);
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s3c2416_irq_add_second();
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return 0;
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}
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static struct subsys_interface s3c2416_irq_interface = {
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.name = "s3c2416_irq",
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.subsys = &s3c2416_subsys,
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.add_dev = s3c2416_irq_add,
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};
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static int __init s3c2416_irq_init(void)
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{
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return subsys_interface_register(&s3c2416_irq_interface);
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}
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arch_initcall(s3c2416_irq_init);
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#ifdef CONFIG_PM
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static struct sleep_save irq_save[] = {
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SAVE_ITEM(S3C2416_INTMSK2),
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};
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int s3c2416_irq_suspend(void)
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{
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s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
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return 0;
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}
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void s3c2416_irq_resume(void)
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{
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s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
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}
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struct syscore_ops s3c2416_irq_syscore_ops = {
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.suspend = s3c2416_irq_suspend,
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.resume = s3c2416_irq_resume,
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};
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#endif
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@ -626,3 +626,289 @@ void __init s3c24xx_init_irq(void)
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s3c24xx_init_intc(NULL, &init_subint[0], main_intc, 0x4a000018);
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s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
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}
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#ifdef CONFIG_CPU_S3C2416
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#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
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static inline void s3c2416_irq_demux(unsigned int irq, unsigned int len)
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{
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unsigned int subsrc, submsk;
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unsigned int end;
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/* read the current pending interrupts, and the mask
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* for what it is available */
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subsrc = __raw_readl(S3C2410_SUBSRCPND);
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submsk = __raw_readl(S3C2410_INTSUBMSK);
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subsrc &= ~submsk;
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subsrc >>= (irq - S3C2410_IRQSUB(0));
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subsrc &= (1 << len)-1;
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end = len + irq;
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for (; irq < end && subsrc; irq++) {
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if (subsrc & 1)
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generic_handle_irq(irq);
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subsrc >>= 1;
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}
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}
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/* WDT/AC97 sub interrupts */
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static void s3c2416_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc)
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{
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s3c2416_irq_demux(IRQ_S3C2443_WDT, 4);
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}
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#define INTMSK_WDTAC97 (1UL << (IRQ_WDT - IRQ_EINT0))
|
||||
#define SUBMSK_WDTAC97 INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97)
|
||||
|
||||
static void s3c2416_irq_wdtac97_mask(struct irq_data *data)
|
||||
{
|
||||
s3c_irqsub_mask(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
|
||||
}
|
||||
|
||||
static void s3c2416_irq_wdtac97_unmask(struct irq_data *data)
|
||||
{
|
||||
s3c_irqsub_unmask(data->irq, INTMSK_WDTAC97);
|
||||
}
|
||||
|
||||
static void s3c2416_irq_wdtac97_ack(struct irq_data *data)
|
||||
{
|
||||
s3c_irqsub_maskack(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
|
||||
}
|
||||
|
||||
static struct irq_chip s3c2416_irq_wdtac97 = {
|
||||
.irq_mask = s3c2416_irq_wdtac97_mask,
|
||||
.irq_unmask = s3c2416_irq_wdtac97_unmask,
|
||||
.irq_ack = s3c2416_irq_wdtac97_ack,
|
||||
};
|
||||
|
||||
/* LCD sub interrupts */
|
||||
|
||||
static void s3c2416_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
s3c2416_irq_demux(IRQ_S3C2443_LCD1, 4);
|
||||
}
|
||||
|
||||
#define INTMSK_LCD (1UL << (IRQ_LCD - IRQ_EINT0))
|
||||
#define SUBMSK_LCD INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4)
|
||||
|
||||
static void s3c2416_irq_lcd_mask(struct irq_data *data)
|
||||
{
|
||||
s3c_irqsub_mask(data->irq, INTMSK_LCD, SUBMSK_LCD);
|
||||
}
|
||||
|
||||
static void s3c2416_irq_lcd_unmask(struct irq_data *data)
|
||||
{
|
||||
s3c_irqsub_unmask(data->irq, INTMSK_LCD);
|
||||
}
|
||||
|
||||
static void s3c2416_irq_lcd_ack(struct irq_data *data)
|
||||
{
|
||||
s3c_irqsub_maskack(data->irq, INTMSK_LCD, SUBMSK_LCD);
|
||||
}
|
||||
|
||||
static struct irq_chip s3c2416_irq_lcd = {
|
||||
.irq_mask = s3c2416_irq_lcd_mask,
|
||||
.irq_unmask = s3c2416_irq_lcd_unmask,
|
||||
.irq_ack = s3c2416_irq_lcd_ack,
|
||||
};
|
||||
|
||||
/* DMA sub interrupts */
|
||||
|
||||
static void s3c2416_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
s3c2416_irq_demux(IRQ_S3C2443_DMA0, 6);
|
||||
}
|
||||
|
||||
#define INTMSK_DMA (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0))
|
||||
#define SUBMSK_DMA INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5)
|
||||
|
||||
|
||||
static void s3c2416_irq_dma_mask(struct irq_data *data)
|
||||
{
|
||||
s3c_irqsub_mask(data->irq, INTMSK_DMA, SUBMSK_DMA);
|
||||
}
|
||||
|
||||
static void s3c2416_irq_dma_unmask(struct irq_data *data)
|
||||
{
|
||||
s3c_irqsub_unmask(data->irq, INTMSK_DMA);
|
||||
}
|
||||
|
||||
static void s3c2416_irq_dma_ack(struct irq_data *data)
|
||||
{
|
||||
s3c_irqsub_maskack(data->irq, INTMSK_DMA, SUBMSK_DMA);
|
||||
}
|
||||
|
||||
static struct irq_chip s3c2416_irq_dma = {
|
||||
.irq_mask = s3c2416_irq_dma_mask,
|
||||
.irq_unmask = s3c2416_irq_dma_unmask,
|
||||
.irq_ack = s3c2416_irq_dma_ack,
|
||||
};
|
||||
|
||||
/* UART3 sub interrupts */
|
||||
|
||||
static void s3c2416_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
s3c2416_irq_demux(IRQ_S3C2443_RX3, 3);
|
||||
}
|
||||
|
||||
#define INTMSK_UART3 (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0))
|
||||
#define SUBMSK_UART3 (0x7 << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0)))
|
||||
|
||||
static void s3c2416_irq_uart3_mask(struct irq_data *data)
|
||||
{
|
||||
s3c_irqsub_mask(data->irq, INTMSK_UART3, SUBMSK_UART3);
|
||||
}
|
||||
|
||||
static void s3c2416_irq_uart3_unmask(struct irq_data *data)
|
||||
{
|
||||
s3c_irqsub_unmask(data->irq, INTMSK_UART3);
|
||||
}
|
||||
|
||||
static void s3c2416_irq_uart3_ack(struct irq_data *data)
|
||||
{
|
||||
s3c_irqsub_maskack(data->irq, INTMSK_UART3, SUBMSK_UART3);
|
||||
}
|
||||
|
||||
static struct irq_chip s3c2416_irq_uart3 = {
|
||||
.irq_mask = s3c2416_irq_uart3_mask,
|
||||
.irq_unmask = s3c2416_irq_uart3_unmask,
|
||||
.irq_ack = s3c2416_irq_uart3_ack,
|
||||
};
|
||||
|
||||
/* second interrupt register */
|
||||
|
||||
static inline void s3c2416_irq_ack_second(struct irq_data *data)
|
||||
{
|
||||
unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D);
|
||||
|
||||
__raw_writel(bitval, S3C2416_SRCPND2);
|
||||
__raw_writel(bitval, S3C2416_INTPND2);
|
||||
}
|
||||
|
||||
static void s3c2416_irq_mask_second(struct irq_data *data)
|
||||
{
|
||||
unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D);
|
||||
unsigned long mask;
|
||||
|
||||
mask = __raw_readl(S3C2416_INTMSK2);
|
||||
mask |= bitval;
|
||||
__raw_writel(mask, S3C2416_INTMSK2);
|
||||
}
|
||||
|
||||
static void s3c2416_irq_unmask_second(struct irq_data *data)
|
||||
{
|
||||
unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D);
|
||||
unsigned long mask;
|
||||
|
||||
mask = __raw_readl(S3C2416_INTMSK2);
|
||||
mask &= ~bitval;
|
||||
__raw_writel(mask, S3C2416_INTMSK2);
|
||||
}
|
||||
|
||||
static struct irq_chip s3c2416_irq_second = {
|
||||
.irq_ack = s3c2416_irq_ack_second,
|
||||
.irq_mask = s3c2416_irq_mask_second,
|
||||
.irq_unmask = s3c2416_irq_unmask_second,
|
||||
};
|
||||
|
||||
|
||||
/* IRQ initialisation code */
|
||||
|
||||
static int s3c2416_add_sub(unsigned int base,
|
||||
void (*demux)(unsigned int,
|
||||
struct irq_desc *),
|
||||
struct irq_chip *chip,
|
||||
unsigned int start, unsigned int end)
|
||||
{
|
||||
unsigned int irqno;
|
||||
|
||||
irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq);
|
||||
irq_set_chained_handler(base, demux);
|
||||
|
||||
for (irqno = start; irqno <= end; irqno++) {
|
||||
irq_set_chip_and_handler(irqno, chip, handle_level_irq);
|
||||
set_irq_flags(irqno, IRQF_VALID);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void s3c2416_irq_add_second(void)
|
||||
{
|
||||
unsigned long pend;
|
||||
unsigned long last;
|
||||
int irqno;
|
||||
int i;
|
||||
|
||||
/* first, clear all interrupts pending... */
|
||||
last = 0;
|
||||
for (i = 0; i < 4; i++) {
|
||||
pend = __raw_readl(S3C2416_INTPND2);
|
||||
|
||||
if (pend == 0 || pend == last)
|
||||
break;
|
||||
|
||||
__raw_writel(pend, S3C2416_SRCPND2);
|
||||
__raw_writel(pend, S3C2416_INTPND2);
|
||||
printk(KERN_INFO "irq: clearing pending status %08x\n",
|
||||
(int)pend);
|
||||
last = pend;
|
||||
}
|
||||
|
||||
for (irqno = IRQ_S3C2416_2D; irqno <= IRQ_S3C2416_I2S1; irqno++) {
|
||||
switch (irqno) {
|
||||
case IRQ_S3C2416_RESERVED2:
|
||||
case IRQ_S3C2416_RESERVED3:
|
||||
/* no IRQ here */
|
||||
break;
|
||||
default:
|
||||
irq_set_chip_and_handler(irqno, &s3c2416_irq_second,
|
||||
handle_edge_irq);
|
||||
set_irq_flags(irqno, IRQF_VALID);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int s3c2416_irq_add(struct device *dev,
|
||||
struct subsys_interface *sif)
|
||||
{
|
||||
printk(KERN_INFO "S3C2416: IRQ Support\n");
|
||||
|
||||
s3c2416_add_sub(IRQ_LCD, s3c2416_irq_demux_lcd, &s3c2416_irq_lcd,
|
||||
IRQ_S3C2443_LCD2, IRQ_S3C2443_LCD4);
|
||||
|
||||
s3c2416_add_sub(IRQ_S3C2443_DMA, s3c2416_irq_demux_dma,
|
||||
&s3c2416_irq_dma, IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5);
|
||||
|
||||
s3c2416_add_sub(IRQ_S3C2443_UART3, s3c2416_irq_demux_uart3,
|
||||
&s3c2416_irq_uart3,
|
||||
IRQ_S3C2443_RX3, IRQ_S3C2443_ERR3);
|
||||
|
||||
s3c2416_add_sub(IRQ_WDT, s3c2416_irq_demux_wdtac97,
|
||||
&s3c2416_irq_wdtac97,
|
||||
IRQ_S3C2443_WDT, IRQ_S3C2443_AC97);
|
||||
|
||||
s3c2416_irq_add_second();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct subsys_interface s3c2416_irq_interface = {
|
||||
.name = "s3c2416_irq",
|
||||
.subsys = &s3c2416_subsys,
|
||||
.add_dev = s3c2416_irq_add,
|
||||
};
|
||||
|
||||
static int __init s3c2416_irq_init(void)
|
||||
{
|
||||
return subsys_interface_register(&s3c2416_irq_interface);
|
||||
}
|
||||
|
||||
arch_initcall(s3c2416_irq_init);
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user