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[MTD] NAND: Alchemy board driver cleanup
- cleaned up the partitions and include files - added more flexible CS and address detection and setup Regression tested on db1200 and db1550. Signed-off-by: Pete Popov <ppopov@pacbell.net> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Pete Popov
Thomas Gleixner
parent
733802d974
commit
ef6f0d1ffc
@ -1,5 +1,5 @@
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# drivers/mtd/nand/Kconfig
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# $Id: Kconfig,v 1.31 2005/06/20 12:03:21 bjd Exp $
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# $Id: Kconfig,v 1.34 2005/09/23 01:44:55 ppopov Exp $
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menu "NAND Flash Device Drivers"
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depends on MTD!=n
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@ -59,8 +59,8 @@ config MTD_NAND_IDS
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tristate
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config MTD_NAND_AU1550
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tristate "Au1550 NAND support"
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depends on SOC_AU1550 && MTD_NAND
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tristate "Au1550/1200 NAND support"
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depends on (SOC_AU1200 || SOC_AU1550) && MTD_NAND
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help
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This enables the driver for the NAND flash controller on the
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AMD/Alchemy 1550 SOC.
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@ -3,7 +3,7 @@
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*
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* Copyright (C) 2004 Embedded Edge, LLC
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*
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* $Id: au1550nd.c,v 1.11 2004/11/04 12:53:10 gleixner Exp $
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* $Id: au1550nd.c,v 1.12 2005/09/23 01:44:55 ppopov Exp $
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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@ -21,13 +21,7 @@
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/* fixme: this is ugly */
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#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 0)
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#include <asm/mach-au1x00/au1000.h>
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#ifdef CONFIG_MIPS_PB1550
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#include <asm/mach-pb1x00/pb1550.h>
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#endif
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#ifdef CONFIG_MIPS_DB1550
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#include <asm/mach-db1x00/db1x00.h>
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#endif
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#include <asm/mach-au1x00/au1xxx.h>
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#else
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#include <asm/au1000.h>
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#ifdef CONFIG_MIPS_PB1550
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@ -45,39 +39,22 @@ static struct mtd_info *au1550_mtd = NULL;
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static void __iomem *p_nand;
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static int nand_width = 1; /* default x8*/
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#define NAND_CS 1
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/*
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* Define partitions for flash device
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*/
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const static struct mtd_partition partition_info[] = {
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#ifdef CONFIG_MIPS_PB1550
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#define NUM_PARTITIONS 2
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{
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.name = "Pb1550 NAND FS 0",
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.name = "NAND FS 0",
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.offset = 0,
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.size = 8*1024*1024
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.size = 8*1024*1024
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},
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{
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.name = "Pb1550 NAND FS 1",
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.name = "NAND FS 1",
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.offset = MTDPART_OFS_APPEND,
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.size = MTDPART_SIZ_FULL
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.size = MTDPART_SIZ_FULL
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}
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#endif
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#ifdef CONFIG_MIPS_DB1550
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#define NUM_PARTITIONS 2
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{
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.name = "Db1550 NAND FS 0",
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.offset = 0,
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.size = 8*1024*1024
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},
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{
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.name = "Db1550 NAND FS 1",
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.offset = MTDPART_OFS_APPEND,
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.size = MTDPART_SIZ_FULL
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}
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#endif
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};
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#define NB_OF(x) (sizeof(x)/sizeof(x[0]))
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/**
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@ -339,11 +316,13 @@ int au1550_device_ready(struct mtd_info *mtd)
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/*
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* Main initialization routine
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*/
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int __init au1550_init (void)
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int __init au1xxx_nand_init (void)
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{
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struct nand_chip *this;
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u16 boot_swapboot = 0; /* default value */
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int retval;
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u32 mem_staddr;
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u32 nand_phys;
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/* Allocate memory for MTD device structure and private data */
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au1550_mtd = kmalloc (sizeof(struct mtd_info) +
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@ -364,8 +343,11 @@ int __init au1550_init (void)
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au1550_mtd->priv = this;
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/* MEM_STNDCTL: disable ints, disable nand boot */
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au_writel(0, MEM_STNDCTL);
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/* disable interrupts */
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au_writel(au_readl(MEM_STNDCTL) & ~(1<<8), MEM_STNDCTL);
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/* disable NAND boot */
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au_writel(au_readl(MEM_STNDCTL) & ~(1<<0), MEM_STNDCTL);
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#ifdef CONFIG_MIPS_PB1550
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/* set gpio206 high */
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@ -397,19 +379,60 @@ int __init au1550_init (void)
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}
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#endif
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/* Configure RCE1 - should be done by YAMON */
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au_writel(0x5 | (nand_width << 22), 0xB4001010); /* MEM_STCFG1 */
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au_writel(NAND_TIMING, 0xB4001014); /* MEM_STTIME1 */
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au_sync();
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/* Configure chip-select; normally done by boot code, e.g. YAMON */
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#ifdef NAND_STCFG
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if (NAND_CS == 0) {
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au_writel(NAND_STCFG, MEM_STCFG0);
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au_writel(NAND_STTIME, MEM_STTIME0);
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au_writel(NAND_STADDR, MEM_STADDR0);
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}
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if (NAND_CS == 1) {
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au_writel(NAND_STCFG, MEM_STCFG1);
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au_writel(NAND_STTIME, MEM_STTIME1);
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au_writel(NAND_STADDR, MEM_STADDR1);
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}
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if (NAND_CS == 2) {
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au_writel(NAND_STCFG, MEM_STCFG2);
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au_writel(NAND_STTIME, MEM_STTIME2);
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au_writel(NAND_STADDR, MEM_STADDR2);
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}
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if (NAND_CS == 3) {
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au_writel(NAND_STCFG, MEM_STCFG3);
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au_writel(NAND_STTIME, MEM_STTIME3);
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au_writel(NAND_STADDR, MEM_STADDR3);
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}
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#endif
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/* Locate NAND chip-select in order to determine NAND phys address */
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mem_staddr = 0x00000000;
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if (((au_readl(MEM_STCFG0) & 0x7) == 0x5) && (NAND_CS == 0))
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mem_staddr = au_readl(MEM_STADDR0);
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else if (((au_readl(MEM_STCFG1) & 0x7) == 0x5) && (NAND_CS == 1))
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mem_staddr = au_readl(MEM_STADDR1);
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else if (((au_readl(MEM_STCFG2) & 0x7) == 0x5) && (NAND_CS == 2))
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mem_staddr = au_readl(MEM_STADDR2);
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else if (((au_readl(MEM_STCFG3) & 0x7) == 0x5) && (NAND_CS == 3))
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mem_staddr = au_readl(MEM_STADDR3);
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/* setup and enable chip select, MEM_STADDR1 */
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/* we really need to decode offsets only up till 0x20 */
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au_writel((1<<28) | (NAND_PHYS_ADDR>>4) |
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(((NAND_PHYS_ADDR + 0x1000)-1) & (0x3fff<<18)>>18),
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MEM_STADDR1);
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au_sync();
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if (mem_staddr == 0x00000000) {
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printk("Au1xxx NAND: ERROR WITH NAND CHIP-SELECT\n");
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kfree(au1550_mtd);
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return 1;
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}
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nand_phys = (mem_staddr << 4) & 0xFFFC0000;
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p_nand = (void __iomem *)ioremap(nand_phys, 0x1000);
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/* make controller and MTD agree */
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if (NAND_CS == 0)
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nand_width = au_readl(MEM_STCFG0) & (1<<22);
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if (NAND_CS == 1)
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nand_width = au_readl(MEM_STCFG1) & (1<<22);
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if (NAND_CS == 2)
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nand_width = au_readl(MEM_STCFG2) & (1<<22);
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if (NAND_CS == 3)
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nand_width = au_readl(MEM_STCFG3) & (1<<22);
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p_nand = ioremap(NAND_PHYS_ADDR, 0x1000);
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/* Set address of hardware control function */
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this->hwcontrol = au1550_hwcontrol;
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@ -438,7 +461,7 @@ int __init au1550_init (void)
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}
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/* Register the partitions */
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add_mtd_partitions(au1550_mtd, partition_info, NUM_PARTITIONS);
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add_mtd_partitions(au1550_mtd, partition_info, NB_OF(partition_info));
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return 0;
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@ -450,7 +473,7 @@ int __init au1550_init (void)
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return retval;
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}
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module_init(au1550_init);
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module_init(au1xxx_nand_init);
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/*
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* Clean up routine
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