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ARM: EXYNOS: add support DMA for EXYNOS4X12 SoC
Signed-off-by: Boojin Kim <boojin.kim@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
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8f7b13218b
commit
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@ -41,6 +41,7 @@ config SOC_EXYNOS4212
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bool "SAMSUNG EXYNOS4212"
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default y
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depends on ARCH_EXYNOS4
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select SAMSUNG_DMADEV
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select S5P_PM if PM
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select S5P_SLEEP if PM
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help
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@ -50,6 +51,7 @@ config SOC_EXYNOS4412
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bool "SAMSUNG EXYNOS4412"
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default y
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depends on ARCH_EXYNOS4
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select SAMSUNG_DMADEV
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help
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Enable EXYNOS4412 SoC support
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@ -333,6 +335,7 @@ config MACH_SMDK4212
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select SAMSUNG_DEV_BACKLIGHT
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select SAMSUNG_DEV_KEYPAD
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select SAMSUNG_DEV_PWM
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select EXYNOS4_DEV_DMA
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select EXYNOS4_SETUP_I2C1
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select EXYNOS4_SETUP_I2C3
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select EXYNOS4_SETUP_I2C7
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@ -29,6 +29,7 @@
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#include <asm/irq.h>
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#include <plat/devs.h>
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#include <plat/irqs.h>
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#include <plat/cpu.h>
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#include <mach/map.h>
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#include <mach/irqs.h>
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@ -36,7 +37,7 @@
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static u64 dma_dmamask = DMA_BIT_MASK(32);
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static u8 pdma0_peri[] = {
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static u8 exynos4210_pdma0_peri[] = {
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DMACH_PCM0_RX,
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DMACH_PCM0_TX,
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DMACH_PCM2_RX,
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@ -69,15 +70,47 @@ static u8 pdma0_peri[] = {
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DMACH_AC97_PCMOUT,
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};
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static struct dma_pl330_platdata exynos4_pdma0_pdata = {
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.nr_valid_peri = ARRAY_SIZE(pdma0_peri),
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.peri_id = pdma0_peri,
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static u8 exynos4212_pdma0_peri[] = {
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DMACH_PCM0_RX,
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DMACH_PCM0_TX,
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DMACH_PCM2_RX,
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DMACH_PCM2_TX,
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DMACH_MIPI_HSI0,
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DMACH_MIPI_HSI1,
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DMACH_SPI0_RX,
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DMACH_SPI0_TX,
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DMACH_SPI2_RX,
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DMACH_SPI2_TX,
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DMACH_I2S0S_TX,
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DMACH_I2S0_RX,
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DMACH_I2S0_TX,
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DMACH_I2S2_RX,
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DMACH_I2S2_TX,
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DMACH_UART0_RX,
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DMACH_UART0_TX,
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DMACH_UART2_RX,
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DMACH_UART2_TX,
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DMACH_UART4_RX,
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DMACH_UART4_TX,
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DMACH_SLIMBUS0_RX,
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DMACH_SLIMBUS0_TX,
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DMACH_SLIMBUS2_RX,
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DMACH_SLIMBUS2_TX,
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DMACH_SLIMBUS4_RX,
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DMACH_SLIMBUS4_TX,
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DMACH_AC97_MICIN,
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DMACH_AC97_PCMIN,
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DMACH_AC97_PCMOUT,
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DMACH_MIPI_HSI4,
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DMACH_MIPI_HSI5,
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};
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struct dma_pl330_platdata exynos4_pdma0_pdata;
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static AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330,
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EXYNOS4_PA_PDMA0, {IRQ_PDMA0}, &exynos4_pdma0_pdata);
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static u8 pdma1_peri[] = {
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static u8 exynos4210_pdma1_peri[] = {
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DMACH_PCM0_RX,
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DMACH_PCM0_TX,
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DMACH_PCM1_RX,
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@ -105,11 +138,41 @@ static u8 pdma1_peri[] = {
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DMACH_SLIMBUS5_TX,
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};
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static struct dma_pl330_platdata exynos4_pdma1_pdata = {
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.nr_valid_peri = ARRAY_SIZE(pdma1_peri),
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.peri_id = pdma1_peri,
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static u8 exynos4212_pdma1_peri[] = {
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DMACH_PCM0_RX,
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DMACH_PCM0_TX,
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DMACH_PCM1_RX,
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DMACH_PCM1_TX,
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DMACH_MIPI_HSI2,
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DMACH_MIPI_HSI3,
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DMACH_SPI1_RX,
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DMACH_SPI1_TX,
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DMACH_I2S0S_TX,
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DMACH_I2S0_RX,
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DMACH_I2S0_TX,
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DMACH_I2S1_RX,
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DMACH_I2S1_TX,
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DMACH_UART0_RX,
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DMACH_UART0_TX,
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DMACH_UART1_RX,
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DMACH_UART1_TX,
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DMACH_UART3_RX,
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DMACH_UART3_TX,
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DMACH_SLIMBUS1_RX,
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DMACH_SLIMBUS1_TX,
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DMACH_SLIMBUS3_RX,
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DMACH_SLIMBUS3_TX,
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DMACH_SLIMBUS5_RX,
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DMACH_SLIMBUS5_TX,
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DMACH_SLIMBUS0AUX_RX,
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DMACH_SLIMBUS0AUX_TX,
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DMACH_SPDIF,
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DMACH_MIPI_HSI6,
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DMACH_MIPI_HSI7,
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};
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static struct dma_pl330_platdata exynos4_pdma1_pdata;
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static AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330,
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EXYNOS4_PA_PDMA1, {IRQ_PDMA1}, &exynos4_pdma1_pdata);
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@ -137,6 +200,22 @@ static int __init exynos4_dma_init(void)
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if (of_have_populated_dt())
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return 0;
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if (soc_is_exynos4210()) {
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exynos4_pdma0_pdata.nr_valid_peri =
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ARRAY_SIZE(exynos4210_pdma0_peri);
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exynos4_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
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exynos4_pdma1_pdata.nr_valid_peri =
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ARRAY_SIZE(exynos4210_pdma1_peri);
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exynos4_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
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} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
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exynos4_pdma0_pdata.nr_valid_peri =
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ARRAY_SIZE(exynos4212_pdma0_peri);
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exynos4_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
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exynos4_pdma1_pdata.nr_valid_peri =
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ARRAY_SIZE(exynos4212_pdma1_peri);
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exynos4_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
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}
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dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask);
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dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask);
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amba_device_register(&exynos4_pdma0_device, &iomem_resource);
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@ -82,6 +82,14 @@ enum dma_ch {
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DMACH_SLIMBUS4_TX,
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DMACH_SLIMBUS5_RX,
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DMACH_SLIMBUS5_TX,
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DMACH_MIPI_HSI0,
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DMACH_MIPI_HSI1,
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DMACH_MIPI_HSI2,
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DMACH_MIPI_HSI3,
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DMACH_MIPI_HSI4,
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DMACH_MIPI_HSI5,
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DMACH_MIPI_HSI6,
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DMACH_MIPI_HSI7,
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DMACH_MTOM_0,
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DMACH_MTOM_1,
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DMACH_MTOM_2,
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