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vxge: Removed unused functions.
- Removed the wrr_rebalance function - This feature is not supported by the ASIC, hence removing the related code. Signed-off-by: Sreenivasa Honnur <sreenivasa.honnur@neterion.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Sreenivasa Honnur
David S. Miller
parent
a4a987d822
commit
f0dfebafcc
@ -460,209 +460,6 @@ __vxge_hw_verify_pci_e_info(struct __vxge_hw_device *hldev)
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return VXGE_HW_OK;
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}
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/*
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* vxge_hw_wrr_rebalance - Rebalance the RX_WRR and KDFC_WRR calandars.
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* Rebalance the RX_WRR and KDFC_WRR calandars.
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*/
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static enum
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vxge_hw_status vxge_hw_wrr_rebalance(struct __vxge_hw_device *hldev)
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{
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u64 val64;
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u32 wrr_states[VXGE_HW_WEIGHTED_RR_SERVICE_STATES];
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u32 i, j, how_often = 1;
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enum vxge_hw_status status = VXGE_HW_OK;
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status = __vxge_hw_device_is_privilaged(hldev->host_type,
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hldev->func_id);
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if (status != VXGE_HW_OK)
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goto exit;
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/* Reset the priorities assigned to the WRR arbitration
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phases for the receive traffic */
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for (i = 0; i < VXGE_HW_WRR_RING_COUNT; i++)
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writeq(0, ((&hldev->mrpcim_reg->rx_w_round_robin_0) + i));
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/* Reset the transmit FIFO servicing calendar for FIFOs */
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for (i = 0; i < VXGE_HW_WRR_FIFO_COUNT; i++) {
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writeq(0, ((&hldev->mrpcim_reg->kdfc_w_round_robin_0) + i));
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writeq(0, ((&hldev->mrpcim_reg->kdfc_w_round_robin_20) + i));
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}
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/* Assign WRR priority 0 for all FIFOs */
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for (i = 1; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
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writeq(VXGE_HW_KDFC_FIFO_0_CTRL_WRR_NUMBER(0),
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((&hldev->mrpcim_reg->kdfc_fifo_0_ctrl) + i));
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writeq(VXGE_HW_KDFC_FIFO_17_CTRL_WRR_NUMBER(0),
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((&hldev->mrpcim_reg->kdfc_fifo_17_ctrl) + i));
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}
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/* Reset to service non-offload doorbells */
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writeq(0, &hldev->mrpcim_reg->kdfc_entry_type_sel_0);
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writeq(0, &hldev->mrpcim_reg->kdfc_entry_type_sel_1);
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/* Set priority 0 to all receive queues */
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writeq(0, &hldev->mrpcim_reg->rx_queue_priority_0);
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writeq(0, &hldev->mrpcim_reg->rx_queue_priority_1);
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writeq(0, &hldev->mrpcim_reg->rx_queue_priority_2);
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/* Initialize all the slots as unused */
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for (i = 0; i < VXGE_HW_WEIGHTED_RR_SERVICE_STATES; i++)
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wrr_states[i] = -1;
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/* Prepare the Fifo service states */
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for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
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if (!hldev->config.vp_config[i].min_bandwidth)
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continue;
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how_often = VXGE_HW_VPATH_BANDWIDTH_MAX /
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hldev->config.vp_config[i].min_bandwidth;
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if (how_often) {
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for (j = 0; j < VXGE_HW_WRR_FIFO_SERVICE_STATES;) {
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if (wrr_states[j] == -1) {
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wrr_states[j] = i;
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/* Make sure each fifo is serviced
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* atleast once */
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if (i == j)
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j += VXGE_HW_MAX_VIRTUAL_PATHS;
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else
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j += how_often;
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} else
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j++;
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}
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}
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}
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/* Fill the unused slots with 0 */
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for (j = 0; j < VXGE_HW_WEIGHTED_RR_SERVICE_STATES; j++) {
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if (wrr_states[j] == -1)
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wrr_states[j] = 0;
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}
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/* Assign WRR priority number for FIFOs */
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for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
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writeq(VXGE_HW_KDFC_FIFO_0_CTRL_WRR_NUMBER(i),
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((&hldev->mrpcim_reg->kdfc_fifo_0_ctrl) + i));
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writeq(VXGE_HW_KDFC_FIFO_17_CTRL_WRR_NUMBER(i),
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((&hldev->mrpcim_reg->kdfc_fifo_17_ctrl) + i));
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}
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/* Modify the servicing algorithm applied to the 3 types of doorbells.
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i.e, none-offload, message and offload */
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writeq(VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_0(0) |
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VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_1(0) |
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VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_2(0) |
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VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_3(0) |
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VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_4(1) |
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VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_5(0) |
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VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_6(0) |
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VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_7(0),
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&hldev->mrpcim_reg->kdfc_entry_type_sel_0);
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writeq(VXGE_HW_KDFC_ENTRY_TYPE_SEL_1_NUMBER_8(1),
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&hldev->mrpcim_reg->kdfc_entry_type_sel_1);
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for (i = 0, j = 0; i < VXGE_HW_WRR_FIFO_COUNT; i++) {
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val64 = VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_0(wrr_states[j++]);
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val64 |= VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_1(wrr_states[j++]);
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val64 |= VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_2(wrr_states[j++]);
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val64 |= VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_3(wrr_states[j++]);
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val64 |= VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_4(wrr_states[j++]);
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val64 |= VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_5(wrr_states[j++]);
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val64 |= VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_6(wrr_states[j++]);
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val64 |= VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_7(wrr_states[j++]);
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writeq(val64, (&hldev->mrpcim_reg->kdfc_w_round_robin_0 + i));
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writeq(val64, (&hldev->mrpcim_reg->kdfc_w_round_robin_20 + i));
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}
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/* Set up the priorities assigned to receive queues */
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writeq(VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_0(0) |
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VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_1(1) |
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VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_2(2) |
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VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_3(3) |
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VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_4(4) |
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VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_5(5) |
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VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_6(6) |
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VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_7(7),
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&hldev->mrpcim_reg->rx_queue_priority_0);
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writeq(VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_8(8) |
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VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_9(9) |
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VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_10(10) |
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VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_11(11) |
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VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_12(12) |
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VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_13(13) |
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VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_14(14) |
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VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_15(15),
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&hldev->mrpcim_reg->rx_queue_priority_1);
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writeq(VXGE_HW_RX_QUEUE_PRIORITY_2_RX_Q_NUMBER_16(16),
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&hldev->mrpcim_reg->rx_queue_priority_2);
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/* Initialize all the slots as unused */
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for (i = 0; i < VXGE_HW_WEIGHTED_RR_SERVICE_STATES; i++)
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wrr_states[i] = -1;
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/* Prepare the Ring service states */
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for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
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if (!hldev->config.vp_config[i].min_bandwidth)
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continue;
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how_often = VXGE_HW_VPATH_BANDWIDTH_MAX /
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hldev->config.vp_config[i].min_bandwidth;
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if (how_often) {
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for (j = 0; j < VXGE_HW_WRR_RING_SERVICE_STATES;) {
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if (wrr_states[j] == -1) {
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wrr_states[j] = i;
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/* Make sure each ring is
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* serviced atleast once */
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if (i == j)
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j += VXGE_HW_MAX_VIRTUAL_PATHS;
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else
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j += how_often;
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} else
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j++;
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}
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}
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}
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/* Fill the unused slots with 0 */
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for (j = 0; j < VXGE_HW_WEIGHTED_RR_SERVICE_STATES; j++) {
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if (wrr_states[j] == -1)
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wrr_states[j] = 0;
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}
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for (i = 0, j = 0; i < VXGE_HW_WRR_RING_COUNT; i++) {
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val64 = VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_0(
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wrr_states[j++]);
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val64 |= VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_1(
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wrr_states[j++]);
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val64 |= VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_2(
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wrr_states[j++]);
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val64 |= VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_3(
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wrr_states[j++]);
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val64 |= VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_4(
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wrr_states[j++]);
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val64 |= VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_5(
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wrr_states[j++]);
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val64 |= VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_6(
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wrr_states[j++]);
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val64 |= VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_7(
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wrr_states[j++]);
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writeq(val64, ((&hldev->mrpcim_reg->rx_w_round_robin_0) + i));
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}
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exit:
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return status;
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}
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/*
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* __vxge_hw_device_initialize
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* Initialize Titan-V hardware.
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@ -679,7 +476,6 @@ enum vxge_hw_status __vxge_hw_device_initialize(struct __vxge_hw_device *hldev)
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goto exit;
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}
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vxge_hw_wrr_rebalance(hldev);
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exit:
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return status;
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}
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