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mtd: nand: split simple ID decode into its own function
When detecting NAND parameters, the code gets a little ugly so that the logic is obscured. Try to remedy that by moving code to separate functions that have well-defined purposes. This patch splits out the simple ID decode functionality, where all the information regarding NAND size/blocksize/pagesize/oobsize/busw is encoded in the first two bytes of the ID string. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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@ -2970,6 +2970,36 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
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}
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}
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/*
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* Old devices have chip data hardcoded in the device ID table. nand_decode_id
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* decodes a matching ID table entry and assigns the MTD size parameters for
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* the chip.
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*/
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static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
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struct nand_flash_dev *type, u8 id_data[8],
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int *busw)
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{
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int maf_id = id_data[0];
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mtd->erasesize = type->erasesize;
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mtd->writesize = type->pagesize;
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mtd->oobsize = mtd->writesize / 32;
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*busw = type->options & NAND_BUSWIDTH_16;
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/*
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* Check for Spansion/AMD ID + repeating 5th, 6th byte since
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* some Spansion chips have erasesize that conflicts with size
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* listed in nand_ids table.
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* Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
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*/
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if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
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&& id_data[6] == 0x00 && id_data[7] == 0x00
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&& mtd->writesize == 512) {
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mtd->erasesize = 128 * 1024;
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mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
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}
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}
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/*
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* Set the bad block marker/indicator (BBM/BBI) patterns according to some
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* heuristic patterns using various detected parameters (e.g., manufacturer,
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@ -3084,26 +3114,7 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
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/* Decode parameters from extended ID */
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nand_decode_ext_id(mtd, chip, id_data, &busw);
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} else {
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/*
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* Old devices have chip data hardcoded in the device id table.
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*/
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mtd->erasesize = type->erasesize;
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mtd->writesize = type->pagesize;
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mtd->oobsize = mtd->writesize / 32;
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busw = type->options & NAND_BUSWIDTH_16;
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/*
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* Check for Spansion/AMD ID + repeating 5th, 6th byte since
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* some Spansion chips have erasesize that conflicts with size
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* listed in nand_ids table.
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* Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
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*/
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if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
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id_data[5] == 0x00 && id_data[6] == 0x00 &&
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id_data[7] == 0x00 && mtd->writesize == 512) {
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mtd->erasesize = 128 * 1024;
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mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
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}
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nand_decode_id(mtd, chip, type, id_data, &busw);
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}
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/* Get chip options */
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chip->options |= type->options;
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