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drm/radeon/kms: add r1xx/r2xx CS support for tiled textures
Not likely this will be implemented anytime soon, but for completeness... Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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c9068eb296
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@ -1558,7 +1558,17 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
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r100_cs_dump_packet(p, pkt);
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r100_cs_dump_packet(p, pkt);
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return r;
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return r;
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}
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}
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ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
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if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
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if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
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tile_flags |= RADEON_TXO_MACRO_TILE;
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if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
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tile_flags |= RADEON_TXO_MICRO_TILE_X2;
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tmp = idx_value & ~(0x7 << 2);
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tmp |= tile_flags;
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ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);
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} else
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ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
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track->textures[i].robj = reloc->robj;
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track->textures[i].robj = reloc->robj;
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track->tex_dirty = true;
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track->tex_dirty = true;
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break;
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break;
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@ -215,7 +215,17 @@ int r200_packet0_check(struct radeon_cs_parser *p,
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r100_cs_dump_packet(p, pkt);
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r100_cs_dump_packet(p, pkt);
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return r;
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return r;
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}
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}
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ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
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if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
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if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
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tile_flags |= R200_TXO_MACRO_TILE;
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if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
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tile_flags |= R200_TXO_MICRO_TILE;
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tmp = idx_value & ~(0x7 << 2);
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tmp |= tile_flags;
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ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);
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} else
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ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
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track->textures[i].robj = reloc->robj;
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track->textures[i].robj = reloc->robj;
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track->tex_dirty = true;
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track->tex_dirty = true;
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break;
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break;
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