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ath9k: Remove a few unused capability macros
Signed-off-by: Sujith <Sujith.Manoharan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -3357,8 +3357,6 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah)
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bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
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u32 capability, u32 *result)
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{
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const struct ath9k_hw_capabilities *pCap = &ah->caps;
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switch (type) {
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case ATH9K_CAP_CIPHER:
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switch (capability) {
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@ -3384,16 +3382,10 @@ bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
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case ATH9K_CAP_TKIP_SPLIT:
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return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
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false : true;
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case ATH9K_CAP_WME_TKIPMIC:
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return 0;
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case ATH9K_CAP_PHYCOUNTERS:
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return ah->has_hw_phycounters ? 0 : -ENXIO;
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case ATH9K_CAP_DIVERSITY:
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return (REG_READ(ah, AR_PHY_CCK_DETECT) &
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AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
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true : false;
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case ATH9K_CAP_PHYDIAG:
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return true;
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case ATH9K_CAP_MCAST_KEYSRCH:
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switch (capability) {
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case 0:
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@ -3408,18 +3400,6 @@ bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
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}
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}
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return false;
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case ATH9K_CAP_TSF_ADJUST:
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return (ah->misc_mode & AR_PCU_TX_ADD_TSF) ?
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true : false;
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case ATH9K_CAP_RFSILENT:
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if (capability == 3)
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return false;
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case ATH9K_CAP_ANT_CFG_2GHZ:
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*result = pCap->num_antcfg_2ghz;
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return true;
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case ATH9K_CAP_ANT_CFG_5GHZ:
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*result = pCap->num_antcfg_5ghz;
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return true;
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case ATH9K_CAP_TXPOW:
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switch (capability) {
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case 0:
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@ -3472,12 +3452,6 @@ bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
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else
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ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
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return true;
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case ATH9K_CAP_TSF_ADJUST:
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if (setting)
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ah->misc_mode |= AR_PCU_TX_ADD_TSF;
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else
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ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
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return true;
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default:
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return false;
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}
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@ -153,16 +153,9 @@ enum ath9k_capability_type {
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ATH9K_CAP_CIPHER = 0,
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ATH9K_CAP_TKIP_MIC,
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ATH9K_CAP_TKIP_SPLIT,
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ATH9K_CAP_PHYCOUNTERS,
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ATH9K_CAP_DIVERSITY,
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ATH9K_CAP_TXPOW,
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ATH9K_CAP_PHYDIAG,
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ATH9K_CAP_MCAST_KEYSRCH,
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ATH9K_CAP_TSF_ADJUST,
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ATH9K_CAP_WME_TKIPMIC,
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ATH9K_CAP_RFSILENT,
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ATH9K_CAP_ANT_CFG_2GHZ,
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ATH9K_CAP_ANT_CFG_5GHZ,
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ATH9K_CAP_DS
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};
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