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block: IBM RamSan 70/80 trivial changes.
This patch includes trivial changes that were recommended by different members of the Linux Community. Changes include: o Removing the redundant wmb(). o Formatting o Various other little things. Signed-off-by: Philip J Kelleher <pjk1939@linux.vnet.ibm.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
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@ -29,10 +29,8 @@
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#include "rsxx_priv.h"
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#include "rsxx_cfg.h"
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static void initialize_config(void *config)
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static void initialize_config(struct rsxx_card_cfg *cfg)
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{
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struct rsxx_card_cfg *cfg = config;
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cfg->hdr.version = RSXX_CFG_VERSION;
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cfg->data.block_size = RSXX_HW_BLK_SIZE;
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@ -181,7 +179,7 @@ int rsxx_load_config(struct rsxx_cardinfo *card)
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} else {
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dev_info(CARD_TO_DEV(card),
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"Initializing card configuration.\n");
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initialize_config(card);
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initialize_config(&card->config);
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st = rsxx_save_config(card);
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if (st)
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return st;
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@ -161,9 +161,9 @@ static irqreturn_t rsxx_isr(int irq, void *pdata)
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}
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/*----------------- Card Event Handler -------------------*/
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static char *rsxx_card_state_to_str(unsigned int state)
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static const char * const rsxx_card_state_to_str(unsigned int state)
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{
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static char *state_strings[] = {
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static const char * const state_strings[] = {
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"Unknown", "Shutdown", "Starting", "Formatting",
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"Uninitialized", "Good", "Shutting Down",
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"Fault", "Read Only Fault", "dStroying"
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@ -126,13 +126,6 @@ static void creg_issue_cmd(struct rsxx_cardinfo *card, struct creg_cmd *cmd)
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cmd->buf, cmd->stream);
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}
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/*
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* Data copy must complete before initiating the command. This is
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* needed for weakly ordered processors (i.e. PowerPC), so that all
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* neccessary registers are written before we kick the hardware.
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*/
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wmb();
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/* Setting the valid bit will kick off the command. */
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iowrite32(cmd->op, card->regmap + CREG_CMD);
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}
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@ -399,12 +392,12 @@ static int __issue_creg_rw(struct rsxx_cardinfo *card,
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return st;
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/*
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* This timeout is neccessary for unresponsive hardware. The additional
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* This timeout is necessary for unresponsive hardware. The additional
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* 20 seconds to used to guarantee that each cregs requests has time to
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* complete.
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*/
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timeout = msecs_to_jiffies((CREG_TIMEOUT_MSEC *
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card->creg_ctrl.q_depth) + 20000);
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timeout = msecs_to_jiffies(CREG_TIMEOUT_MSEC *
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card->creg_ctrl.q_depth + 20000);
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/*
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* The creg interface is guaranteed to complete. It has a timeout
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@ -432,16 +432,6 @@ static void rsxx_issue_dmas(struct work_struct *work)
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/* Let HW know we've queued commands. */
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if (cmds_pending) {
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/*
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* We must guarantee that the CPU writes to 'ctrl->cmd.buf'
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* (which is in PCI-consistent system-memory) from the loop
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* above make it into the coherency domain before the
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* following PIO "trigger" updating the cmd.idx. A WMB is
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* sufficient. We need not explicitly CPU cache-flush since
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* the memory is a PCI-consistent (ie; coherent) mapping.
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*/
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wmb();
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atomic_add(cmds_pending, &ctrl->stats.hw_q_depth);
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mod_timer(&ctrl->activity_timer,
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jiffies + DMA_ACTIVITY_TIMEOUT);
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@ -798,8 +788,6 @@ static int rsxx_dma_ctrl_init(struct pci_dev *dev,
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iowrite32(ctrl->cmd.idx, ctrl->regmap + HW_CMD_IDX);
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iowrite32(ctrl->cmd.idx, ctrl->regmap + SW_CMD_IDX);
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wmb();
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return 0;
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}
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@ -27,15 +27,17 @@
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/*----------------- IOCTL Definitions -------------------*/
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#define RSXX_MAX_DATA 8
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struct rsxx_reg_access {
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__u32 addr;
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__u32 cnt;
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__u32 stat;
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__u32 stream;
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__u32 data[8];
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__u32 data[RSXX_MAX_DATA];
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};
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#define RSXX_MAX_REG_CNT (8 * (sizeof(__u32)))
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#define RSXX_MAX_REG_CNT (RSXX_MAX_DATA * (sizeof(__u32)))
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#define RSXX_IOC_MAGIC 'r'
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