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clk: sunxi-ng: add missing hdmi-slow clock for H6 CCU
The Allwinner H6 CCU has a "HDMI Slow Clock", which is currently missing in the ccu-sun50i-h6 driver. Add this missing clock to the driver. Fixes: 542353ea ("clk: sunxi-ng: add support for the Allwinner H6 CCU") Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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@ -643,6 +643,8 @@ static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents, 0xb00,
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BIT(31), /* gate */
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0);
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static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0xb04, BIT(31), 0);
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static const char * const hdmi_cec_parents[] = { "osc32k", "pll-periph0-2x" };
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static const struct ccu_mux_fixed_prediv hdmi_cec_predivs[] = {
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{ .index = 1, .div = 36621 },
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@ -876,6 +878,7 @@ static struct ccu_common *sun50i_h6_ccu_clks[] = {
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&pcie_aux_clk.common,
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&bus_pcie_clk.common,
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&hdmi_clk.common,
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&hdmi_slow_clk.common,
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&hdmi_cec_clk.common,
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&bus_hdmi_clk.common,
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&bus_tcon_top_clk.common,
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@ -1017,6 +1020,7 @@ static struct clk_hw_onecell_data sun50i_h6_hw_clks = {
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[CLK_PCIE_AUX] = &pcie_aux_clk.common.hw,
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[CLK_BUS_PCIE] = &bus_pcie_clk.common.hw,
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[CLK_HDMI] = &hdmi_clk.common.hw,
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[CLK_HDMI_SLOW] = &hdmi_slow_clk.common.hw,
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[CLK_HDMI_CEC] = &hdmi_cec_clk.common.hw,
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[CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
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[CLK_BUS_TCON_TOP] = &bus_tcon_top_clk.common.hw,
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@ -51,6 +51,6 @@
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#define CLK_BUS_DRAM 60
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#define CLK_NUMBER 137
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#define CLK_NUMBER (CLK_BUS_HDCP + 1)
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#endif /* _CCU_SUN50I_H6_H_ */
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@ -107,18 +107,19 @@
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#define CLK_PCIE_AUX 121
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#define CLK_BUS_PCIE 122
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#define CLK_HDMI 123
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#define CLK_HDMI_CEC 124
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#define CLK_BUS_HDMI 125
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#define CLK_BUS_TCON_TOP 126
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#define CLK_TCON_LCD0 127
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#define CLK_BUS_TCON_LCD0 128
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#define CLK_TCON_TV0 129
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#define CLK_BUS_TCON_TV0 130
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#define CLK_CSI_CCI 131
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#define CLK_CSI_TOP 132
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#define CLK_CSI_MCLK 133
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#define CLK_BUS_CSI 134
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#define CLK_HDCP 135
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#define CLK_BUS_HDCP 136
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#define CLK_HDMI_SLOW 124
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#define CLK_HDMI_CEC 125
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#define CLK_BUS_HDMI 126
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#define CLK_BUS_TCON_TOP 127
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#define CLK_TCON_LCD0 128
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#define CLK_BUS_TCON_LCD0 129
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#define CLK_TCON_TV0 130
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#define CLK_BUS_TCON_TV0 131
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#define CLK_CSI_CCI 132
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#define CLK_CSI_TOP 133
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#define CLK_CSI_MCLK 134
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#define CLK_BUS_CSI 135
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#define CLK_HDCP 136
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#define CLK_BUS_HDCP 137
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#endif /* _DT_BINDINGS_CLK_SUN50I_H6_H_ */
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