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ARM: OMAP: gpmc: enable hwecc for AM33xx SoCs
The am33xx is capable of handling bch error correction modes, so enable that feature in the driver. Signed-off-by: Daniel Mack <zonque@gmail.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -92,17 +92,18 @@ static int omap2_nand_gpmc_retime(
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static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
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{
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/* support only OMAP3 class */
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if (!cpu_is_omap34xx()) {
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if (!cpu_is_omap34xx() && !soc_is_am33xx()) {
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pr_err("BCH ecc is not supported on this CPU\n");
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return 0;
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}
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/*
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* For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1.
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* Other chips may be added if confirmed to work.
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* For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1
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* and AM33xx derivates. Other chips may be added if confirmed to work.
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*/
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if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) &&
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(!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) {
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(!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)) &&
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(!soc_is_am33xx())) {
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pr_err("BCH 4-bit mode is not supported on this CPU\n");
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return 0;
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}
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