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blackfin updates for Linux 3.10

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Merge tag 'for-linus' of git://github.com/realmz/blackfin-linux

Pull blackfin updates from Steven Miao.

* tag 'for-linus' of git://github.com/realmz/blackfin-linux:
  bfin cache: dcplb map: add 16M dcplb map for BF60x
  blackfin: smp: fix smp build after drop asm/system.h
  blackfin: fix bootup core clock and system clock display
  Platform Nand: Set the GPIO for NAND read as input
  blackfin: rename vmImage to uImage after we move to buildroot
  blackfin: twi: Remove bogus #endif
  bf609: rsi: Add bf609 rsi MMR macro and board platform data.
  blackfin: dmc: Improve DDR2 write through in DMC effict controller.
This commit is contained in:
Linus Torvalds 2013-05-10 07:21:16 -07:00
commit f5b8fcb48b
14 changed files with 101 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/blackfin/Makefile
View File

@ -141,11 +141,11 @@ archclean:
INSTALL_PATH ?= /tftpboot
boot := arch/$(ARCH)/boot
BOOT_TARGETS = vmImage vmImage.bin vmImage.bz2 vmImage.gz vmImage.lzma vmImage.lzo vmImage.xip
BOOT_TARGETS = uImage uImage.bin uImage.bz2 uImage.gz uImage.lzma uImage.lzo uImage.xip
PHONY += $(BOOT_TARGETS) install
KBUILD_IMAGE := $(boot)/vmImage
KBUILD_IMAGE := $(boot)/uImage
all: vmImage
all: uImage
$(BOOT_TARGETS): vmlinux
$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@

16
arch/blackfin/boot/Makefile
View File

@ -6,7 +6,7 @@
# for more details.
#
targets := vmImage vmImage.bin vmImage.bz2 vmImage.gz vmImage.lzma vmImage.lzo vmImage.xip
targets := uImage uImage.bin uImage.bz2 uImage.gz uImage.lzma uImage.lzo uImage.xip
extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma vmlinux.bin.lzo vmlinux.bin.xip
ifeq ($(CONFIG_RAMKERNEL),y)
@ -39,22 +39,22 @@ quiet_cmd_mk_bin_xip = BIN $@
$(obj)/vmlinux.bin.xip: $(obj)/vmlinux.bin FORCE
$(call if_changed,mk_bin_xip)
$(obj)/vmImage.bin: $(obj)/vmlinux.bin
$(obj)/uImage.bin: $(obj)/vmlinux.bin
$(call if_changed,uimage,none)
$(obj)/vmImage.bz2: $(obj)/vmlinux.bin.bz2
$(obj)/uImage.bz2: $(obj)/vmlinux.bin.bz2
$(call if_changed,uimage,bzip2)
$(obj)/vmImage.gz: $(obj)/vmlinux.bin.gz
$(obj)/uImage.gz: $(obj)/vmlinux.bin.gz
$(call if_changed,uimage,gzip)
$(obj)/vmImage.lzma: $(obj)/vmlinux.bin.lzma
$(obj)/uImage.lzma: $(obj)/vmlinux.bin.lzma
$(call if_changed,uimage,lzma)
$(obj)/vmImage.lzo: $(obj)/vmlinux.bin.lzo
$(obj)/uImage.lzo: $(obj)/vmlinux.bin.lzo
$(call if_changed,uimage,lzo)
$(obj)/vmImage.xip: $(obj)/vmlinux.bin.xip
$(obj)/uImage.xip: $(obj)/vmlinux.bin.xip
$(call if_changed,uimage,none)
suffix-y := bin
@ -64,7 +64,7 @@ suffix-$(CONFIG_KERNEL_LZMA) := lzma
suffix-$(CONFIG_KERNEL_LZO) := lzo
suffix-$(CONFIG_ROMKERNEL) := xip
$(obj)/vmImage: $(obj)/vmImage.$(suffix-y)
$(obj)/uImage: $(obj)/uImage.$(suffix-y)
@ln -sf $(notdir $<) $@
install:

2
arch/blackfin/include/asm/atomic.h
View File

@ -11,7 +11,9 @@
#ifdef CONFIG_SMP
#include <asm/barrier.h>
#include <linux/linkage.h>
#include <linux/types.h>
asmlinkage int __raw_uncached_fetch_asm(const volatile int *ptr);
asmlinkage int __raw_atomic_update_asm(volatile int *ptr, int value);

31
arch/blackfin/include/asm/bfin_sdh.h
View File

@ -24,18 +24,27 @@ struct bfin_sd_host {
#define CMD_INT_E (1 << 8) /* Command Interrupt */
#define CMD_PEND_E (1 << 9) /* Command Pending */
#define CMD_E (1 << 10) /* Command Enable */
#ifdef RSI_BLKSZ
#define CMD_CRC_CHECK_D (1 << 11) /* CRC Check is disabled */
#define CMD_DATA0_BUSY (1 << 12) /* Check for Busy State on the DATA0 pin */
#endif
/* SDH_PWR_CTL bitmasks */
#ifndef RSI_BLKSZ
#define PWR_ON 0x3 /* Power On */
#define SD_CMD_OD (1 << 6) /* Open Drain Output */
#define ROD_CTL (1 << 7) /* Rod Control */
#endif
/* SDH_CLK_CTL bitmasks */
#define CLKDIV 0xff /* MC_CLK Divisor */
#define CLK_E (1 << 8) /* MC_CLK Bus Clock Enable */
#define PWR_SV_E (1 << 9) /* Power Save Enable */
#define CLKDIV_BYPASS (1 << 10) /* Bypass Divisor */
#define WIDE_BUS (1 << 11) /* Wide Bus Mode Enable */
#define BUS_MODE_MASK 0x1800 /* Bus Mode Mask */
#define STD_BUS_1 0x000 /* Standard Bus 1 bit mode */
#define WIDE_BUS_4 0x800 /* Wide Bus 4 bit mode */
#define BYTE_BUS_8 0x1000 /* Byte Bus 8 bit mode */
/* SDH_RESP_CMD bitmasks */
#define RESP_CMD 0x3f /* Response Command */
@ -45,7 +54,13 @@ struct bfin_sd_host {
#define DTX_DIR (1 << 1) /* Data Transfer Direction */
#define DTX_MODE (1 << 2) /* Data Transfer Mode */
#define DTX_DMA_E (1 << 3) /* Data Transfer DMA Enable */
#ifndef RSI_BLKSZ
#define DTX_BLK_LGTH (0xf << 4) /* Data Transfer Block Length */
#else
/* Bit masks for SDH_BLK_SIZE */
#define DTX_BLK_LGTH 0x1fff /* Data Transfer Block Length */
#endif
/* SDH_STATUS bitmasks */
#define CMD_CRC_FAIL (1 << 0) /* CMD CRC Fail */
@ -114,10 +129,14 @@ struct bfin_sd_host {
/* SDH_E_STATUS bitmasks */
#define SDIO_INT_DET (1 << 1) /* SDIO Int Detected */
#define SD_CARD_DET (1 << 4) /* SD Card Detect */
#define SD_CARD_BUSYMODE (1 << 31) /* Card is in Busy mode */
#define SD_CARD_SLPMODE (1 << 30) /* Card in Sleep Mode */
#define SD_CARD_READY (1 << 17) /* Card Ready */
/* SDH_E_MASK bitmasks */
#define SDIO_MSK (1 << 1) /* Mask SDIO Int Detected */
#define SCD_MSK (1 << 6) /* Mask Card Detect */
#define SCD_MSK (1 << 4) /* Mask Card Detect */
#define CARD_READY_MSK (1 << 16) /* Mask Card Ready */
/* SDH_CFG bitmasks */
#define CLKS_EN (1 << 0) /* Clocks Enable */
@ -126,7 +145,15 @@ struct bfin_sd_host {
#define SD_RST (1 << 4) /* SDMMC Reset */
#define PUP_SDDAT (1 << 5) /* Pull-up SD_DAT */
#define PUP_SDDAT3 (1 << 6) /* Pull-up SD_DAT3 */
#ifndef RSI_BLKSZ
#define PD_SDDAT3 (1 << 7) /* Pull-down SD_DAT3 */
#else
#define PWR_ON 0x600 /* Power On */
#define SD_CMD_OD (1 << 11) /* Open Drain Output */
#define BOOT_EN (1 << 12) /* Boot Enable */
#define BOOT_MODE (1 << 13) /* Alternate Boot Mode */
#define BOOT_ACK_EN (1 << 14) /* Boot ACK is expected */
#endif
/* SDH_RD_WAIT_EN bitmasks */
#define RWR (1 << 0) /* Read Wait Request */

1
arch/blackfin/include/asm/bitops.h
View File

@ -41,6 +41,7 @@
#include <asm-generic/bitops/non-atomic.h>
#else
#include <asm/barrier.h>
#include <asm/byteorder.h> /* swab32 */
#include <linux/linkage.h>

2
arch/blackfin/include/asm/def_LPBlackfin.h
View File

@ -622,10 +622,12 @@ do { \
#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */
#ifdef CONFIG_BF60x
#define PAGE_SIZE_16KB 0x00040000 /* 16 KB page size */
#define PAGE_SIZE_64KB 0x00050000 /* 64 KB page size */
#define PAGE_SIZE_16MB 0x00060000 /* 16 MB page size */
#define PAGE_SIZE_64MB 0x00070000 /* 64 MB page size */
#endif
#define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not
* mapped to L1
*/

9
arch/blackfin/include/asm/mem_init.h
View File

@ -335,6 +335,7 @@
struct ddr_config {
u32 ddr_clk;
u32 dmc_ddrctl;
u32 dmc_effctl;
u32 dmc_ddrcfg;
u32 dmc_ddrtr0;
u32 dmc_ddrtr1;
@ -348,6 +349,7 @@ static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1")))
[0] = {
.ddr_clk = 125,
.dmc_ddrctl = 0x00000904,
.dmc_effctl = 0x004400C0,
.dmc_ddrcfg = 0x00000422,
.dmc_ddrtr0 = 0x20705212,
.dmc_ddrtr1 = 0x201003CF,
@ -358,6 +360,7 @@ static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1")))
[1] = {
.ddr_clk = 133,
.dmc_ddrctl = 0x00000904,
.dmc_effctl = 0x004400C0,
.dmc_ddrcfg = 0x00000422,
.dmc_ddrtr0 = 0x20806313,
.dmc_ddrtr1 = 0x2013040D,
@ -368,6 +371,7 @@ static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1")))
[2] = {
.ddr_clk = 150,
.dmc_ddrctl = 0x00000904,
.dmc_effctl = 0x004400C0,
.dmc_ddrcfg = 0x00000422,
.dmc_ddrtr0 = 0x20A07323,
.dmc_ddrtr1 = 0x20160492,
@ -378,6 +382,7 @@ static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1")))
[3] = {
.ddr_clk = 166,
.dmc_ddrctl = 0x00000904,
.dmc_effctl = 0x004400C0,
.dmc_ddrcfg = 0x00000422,
.dmc_ddrtr0 = 0x20A07323,
.dmc_ddrtr1 = 0x2016050E,
@ -388,6 +393,7 @@ static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1")))
[4] = {
.ddr_clk = 200,
.dmc_ddrctl = 0x00000904,
.dmc_effctl = 0x004400C0,
.dmc_ddrcfg = 0x00000422,
.dmc_ddrtr0 = 0x20a07323,
.dmc_ddrtr1 = 0x2016050f,
@ -398,6 +404,7 @@ static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1")))
[5] = {
.ddr_clk = 225,
.dmc_ddrctl = 0x00000904,
.dmc_effctl = 0x004400C0,
.dmc_ddrcfg = 0x00000422,
.dmc_ddrtr0 = 0x20E0A424,
.dmc_ddrtr1 = 0x302006DB,
@ -408,6 +415,7 @@ static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1")))
[6] = {
.ddr_clk = 250,
.dmc_ddrctl = 0x00000904,
.dmc_effctl = 0x004400C0,
.dmc_ddrcfg = 0x00000422,
.dmc_ddrtr0 = 0x20E0A424,
.dmc_ddrtr1 = 0x3020079E,
@ -469,6 +477,7 @@ static inline void init_dmc(u32 dmc_clk)
bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2);
bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr);
bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1);
bfin_write_DMC0_EFFCTL(ddr_config_table[i].dmc_effctl);
bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl);
break;
}

16
arch/blackfin/kernel/cplb-nompu/cplbinit.c
View File

@ -30,6 +30,7 @@ void __init generate_cplb_tables_cpu(unsigned int cpu)
{
int i_d, i_i;
unsigned long addr;
unsigned long cplb_pageflags, cplb_pagesize;
struct cplb_entry *d_tbl = dcplb_tbl[cpu];
struct cplb_entry *i_tbl = icplb_tbl[cpu];
@ -49,11 +50,20 @@ void __init generate_cplb_tables_cpu(unsigned int cpu)
/* Cover kernel memory with 4M pages. */
addr = 0;
for (; addr < memory_start; addr += 4 * 1024 * 1024) {
#ifdef PAGE_SIZE_16MB
cplb_pageflags = PAGE_SIZE_16MB;
cplb_pagesize = SIZE_16M;
#else
cplb_pageflags = PAGE_SIZE_4MB;
cplb_pagesize = SIZE_4M;
#endif
for (; addr < memory_start; addr += cplb_pagesize) {
d_tbl[i_d].addr = addr;
d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_4MB;
d_tbl[i_d++].data = SDRAM_DGENERIC | cplb_pageflags;
i_tbl[i_i].addr = addr;
i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_4MB;
i_tbl[i_i++].data = SDRAM_IGENERIC | cplb_pageflags;
}
#ifdef CONFIG_ROMKERNEL

27
arch/blackfin/kernel/cplb-nompu/cplbmgr.c
View File

@ -145,7 +145,7 @@ MGR_ATTR static int dcplb_miss(int cpu)
unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();
int status = bfin_read_DCPLB_STATUS();
int idx;
unsigned long d_data, base, addr1, eaddr;
unsigned long d_data, base, addr1, eaddr, cplb_pagesize, cplb_pageflags;
nr_dcplb_miss[cpu]++;
if (unlikely(status & FAULT_USERSUPV))
@ -167,18 +167,37 @@ MGR_ATTR static int dcplb_miss(int cpu)
if (unlikely(d_data == 0))
return CPLB_NO_ADDR_MATCH;
addr1 = addr & ~(SIZE_4M - 1);
addr &= ~(SIZE_1M - 1);
d_data |= PAGE_SIZE_1MB;
if (addr1 >= base && (addr1 + SIZE_4M) <= eaddr) {
/* BF60x support large than 4M CPLB page size */
#ifdef PAGE_SIZE_16MB
cplb_pageflags = PAGE_SIZE_16MB;
cplb_pagesize = SIZE_16M;
#else
cplb_pageflags = PAGE_SIZE_4MB;
cplb_pagesize = SIZE_4M;
#endif
find_pagesize:
addr1 = addr & ~(cplb_pagesize - 1);
if (addr1 >= base && (addr1 + cplb_pagesize) <= eaddr) {
/*
* This works because
* (PAGE_SIZE_4MB & PAGE_SIZE_1MB) == PAGE_SIZE_1MB.
*/
d_data |= PAGE_SIZE_4MB;
d_data |= cplb_pageflags;
addr = addr1;
goto found_pagesize;
} else {
if (cplb_pagesize > SIZE_4M) {
cplb_pageflags = PAGE_SIZE_4MB;
cplb_pagesize = SIZE_4M;
goto find_pagesize;
}
}
found_pagesize:
#ifdef CONFIG_BF60x
if ((addr >= ASYNC_BANK0_BASE)
&& (addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE))

9
arch/blackfin/kernel/cplbinfo.c
View File

@ -17,8 +17,13 @@
#include <asm/cplbinit.h>
#include <asm/blackfin.h>
static char const page_strtbl[][3] = { "1K", "4K", "1M", "4M" };
#define page(flags) (((flags) & 0x30000) >> 16)
static char const page_strtbl[][4] = {
"1K", "4K", "1M", "4M",
#ifdef CONFIG_BF60x
"16K", "64K", "16M", "64M",
#endif
};
#define page(flags) (((flags) & 0x70000) >> 16)
#define strpage(flags) page_strtbl[page(flags)]
struct cplbinfo_data {

2
arch/blackfin/kernel/setup.c
View File

@ -1314,7 +1314,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
seq_printf(m, "(Compiled for Rev %d)", bfin_compiled_revid());
}
seq_printf(m, "\ncpu MHz\t\t: %lu.%03lu/%lu.%03lu\n",
seq_printf(m, "\ncpu MHz\t\t: %lu.%06lu/%lu.%06lu\n",
cclk/1000000, cclk%1000000,
sclk/1000000, sclk%1000000);
seq_printf(m, "bogomips\t: %lu.%02lu\n"

1
arch/blackfin/mach-bf537/boards/stamp.c
View File

@ -455,6 +455,7 @@ static struct platform_device bfin_async_nand_device = {
static void bfin_plat_nand_init(void)
{
gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat");
gpio_direction_input(BFIN_NAND_PLAT_READY);
}
#else
static void bfin_plat_nand_init(void) {}

1
arch/blackfin/mach-bf538/boards/ezkit.c
View File

@ -764,7 +764,6 @@ static struct platform_device i2c_bfin_twi1_device = {
.num_resources = ARRAY_SIZE(bfin_twi1_resource),
.resource = bfin_twi1_resource,
};
#endif /* CONFIG_BF542 */
#endif /* CONFIG_I2C_BLACKFIN_TWI */
#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)

2
arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h
View File

@ -312,6 +312,8 @@
#define bfin_write_DMC0_EMR1(val) bfin_write32(DMC0_EMR1, val)
#define bfin_read_DMC0_CTL() bfin_read32(DMC0_CTL)
#define bfin_write_DMC0_CTL(val) bfin_write32(DMC0_CTL, val)
#define bfin_read_DMC0_EFFCTL() bfin_read32(DMC0_EFFCTL)
#define bfin_write_DMC0_EFFCTL(val) bfin_write32(DMC0_EFFCTL, val)
#define bfin_read_DMC0_STAT() bfin_read32(DMC0_STAT)
#define bfin_write_DMC0_STAT(val) bfin_write32(DMC0_STAT, val)
#define bfin_read_DMC0_DLLCTL() bfin_read32(DMC0_DLLCTL)