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[MIPS] Fix shadow register support.
Shadow register support would not possibly have worked on multicore systems. The support code for it was also depending not on MIPS R2 but VSMP or SMTC kernels even though it makes perfect sense with UP kernels. SR sets are a scarce resource and the expected usage pattern is that users actually hardcode the register set numbers in their code. So fix the allocator by ditching it. Move the remaining CPU probe bits into the generic CPU probe. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
parent
efb9ca08b5
commit
f6771dbb27
@ -1409,7 +1409,6 @@ config MIPS_MT_SMP
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depends on SYS_SUPPORTS_MULTITHREADING
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select CPU_MIPSR2_IRQ_VI
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select CPU_MIPSR2_IRQ_EI
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select CPU_MIPSR2_SRS
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select MIPS_MT
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select NR_CPUS_DEFAULT_2
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select SMP
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@ -1426,7 +1425,6 @@ config MIPS_MT_SMTC
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select GENERIC_CLOCKEVENTS_BROADCAST
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select CPU_MIPSR2_IRQ_VI
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select CPU_MIPSR2_IRQ_EI
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select CPU_MIPSR2_SRS
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select MIPS_MT
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select NR_CPUS_DEFAULT_8
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select SMP
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@ -1453,7 +1451,6 @@ config MIPS_VPE_LOADER
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depends on SYS_SUPPORTS_MULTITHREADING
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select CPU_MIPSR2_IRQ_VI
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select CPU_MIPSR2_IRQ_EI
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select CPU_MIPSR2_SRS
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select MIPS_MT
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help
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Includes a loader for loading an elf relocatable object
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@ -1582,12 +1579,6 @@ config CPU_MIPSR2_IRQ_VI
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config CPU_MIPSR2_IRQ_EI
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bool
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#
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# Shadow registers are an R2 feature
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#
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config CPU_MIPSR2_SRS
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bool
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config CPU_HAS_SYNC
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bool
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depends on !CPU_R3000
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@ -943,6 +943,11 @@ __init void cpu_probe(void)
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}
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__cpu_name[cpu] = cpu_to_name(c);
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if (cpu_has_mips_r2)
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c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
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else
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c->srsets = 1;
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}
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__init void cpu_report(void)
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@ -60,6 +60,8 @@ static int show_cpuinfo(struct seq_file *m, void *v)
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cpu_has_dsp ? " dsp" : "",
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cpu_has_mipsmt ? " mt" : ""
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);
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seq_printf(m, "shadow register sets\t: %d\n",
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cpu_data[n].srsets);
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sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
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cpu_has_vce ? "%u" : "not available");
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@ -1100,59 +1100,6 @@ void *set_except_vector(int n, void *addr)
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return (void *)old_handler;
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}
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#ifdef CONFIG_CPU_MIPSR2_SRS
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/*
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* MIPSR2 shadow register set allocation
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* FIXME: SMP...
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*/
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static struct shadow_registers {
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/*
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* Number of shadow register sets supported
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*/
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unsigned long sr_supported;
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/*
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* Bitmap of allocated shadow registers
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*/
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unsigned long sr_allocated;
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} shadow_registers;
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static void mips_srs_init(void)
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{
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shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
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printk(KERN_INFO "%ld MIPSR2 register sets available\n",
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shadow_registers.sr_supported);
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shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */
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}
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int mips_srs_max(void)
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{
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return shadow_registers.sr_supported;
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}
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int mips_srs_alloc(void)
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{
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struct shadow_registers *sr = &shadow_registers;
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int set;
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again:
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set = find_first_zero_bit(&sr->sr_allocated, sr->sr_supported);
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if (set >= sr->sr_supported)
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return -1;
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if (test_and_set_bit(set, &sr->sr_allocated))
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goto again;
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return set;
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}
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void mips_srs_free(int set)
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{
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struct shadow_registers *sr = &shadow_registers;
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clear_bit(set, &sr->sr_allocated);
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}
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static asmlinkage void do_default_vi(void)
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{
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show_regs(get_irq_regs());
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@ -1163,6 +1110,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
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{
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unsigned long handler;
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unsigned long old_handler = vi_handlers[n];
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int srssets = current_cpu_data.srsets;
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u32 *w;
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unsigned char *b;
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@ -1178,7 +1126,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
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b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
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if (srs >= mips_srs_max())
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if (srs >= srssets)
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panic("Shadow register set %d not supported", srs);
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if (cpu_has_veic) {
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@ -1186,7 +1134,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
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board_bind_eic_interrupt(n, srs);
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} else if (cpu_has_vint) {
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/* SRSMap is only defined if shadow sets are implemented */
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if (mips_srs_max() > 1)
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if (srssets > 1)
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change_c0_srsmap(0xf << n*4, srs << n*4);
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}
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@ -1253,14 +1201,6 @@ void *set_vi_handler(int n, vi_handler_t addr)
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return set_vi_srs_handler(n, addr, 0);
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}
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#else
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static inline void mips_srs_init(void)
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{
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}
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#endif /* CONFIG_CPU_MIPSR2_SRS */
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/*
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* This is used by native signal handling
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*/
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@ -1503,8 +1443,6 @@ void __init trap_init(void)
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else
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ebase = CAC_BASE;
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mips_srs_init();
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per_cpu_trap_init();
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/*
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@ -54,6 +54,7 @@ struct cpuinfo_mips {
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struct cache_desc dcache; /* Primary D or combined I/D cache */
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struct cache_desc scache; /* Secondary cache */
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struct cache_desc tcache; /* Tertiary/split secondary cache */
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int srsets; /* Shadow register sets */
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#if defined(CONFIG_MIPS_MT_SMTC)
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/*
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* In the MIPS MT "SMTC" model, each TC is considered
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