mirror of
https://github.com/FEX-Emu/linux.git
synced 2024-12-20 08:22:39 +00:00
Merge branch 'drm-radeon-fusion' of ../drm-radeon-next into drm-core-next
* 'drm-radeon-fusion' of ../drm-radeon-next: drm/radeon/kms: add Ontario APU ucode loading support drm/radeon/kms: add Ontario Fusion APU pci ids drm/radeon/kms: enable MSIs on fusion APUs drm/radeon/kms: add power table parsing support for Ontario fusion APUs drm/radeon/kms: refactor atombios power state fetching drm/radeon/kms: add bo blit support for Ontario fusion APUs drm/radeon/kms: add thermal sensor support for fusion APUs drm/radeon/kms: fill in GPU init for AMD Ontario Fusion APUs drm/radeon/kms: add radeon_asic struct for AMD Ontario fusion APUs drm/radeon/kms: evergreen.c updates for fusion drm/radeon/kms: MC setup changes for fusion APUs drm/radeon/kms: move r7xx/evergreen to its own vram_gtt setup function drm/radeon/kms: add support for ss overrides on Fusion APUs drm/radeon/kms: Add support for external encoders on fusion APUs drm/radeon/kms: atom changes for DCE4.1 devices drm/radeon/kms: add new family id for AMD Ontario APUs drm/radeon/kms: upstream power table updates drm/radeon/kms: upstream atombios.h updates drm/radeon/kms: upstream ObjectID.h updates drm/radeon/kms: setup mc chremap properly on r7xx/evergreen
This commit is contained in:
Dave Airlie
commit
f7eb0c5541
@ -37,6 +37,8 @@
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#define GRAPH_OBJECT_TYPE_CONNECTOR 0x3
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#define GRAPH_OBJECT_TYPE_ROUTER 0x4
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/* deleted */
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#define GRAPH_OBJECT_TYPE_DISPLAY_PATH 0x6
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#define GRAPH_OBJECT_TYPE_GENERIC 0x7
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/****************************************************/
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/* Encoder Object ID Definition */
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@ -64,6 +66,9 @@
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#define ENCODER_OBJECT_ID_VT1623 0x10
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#define ENCODER_OBJECT_ID_HDMI_SI1930 0x11
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#define ENCODER_OBJECT_ID_HDMI_INTERNAL 0x12
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#define ENCODER_OBJECT_ID_ALMOND 0x22
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#define ENCODER_OBJECT_ID_TRAVIS 0x23
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#define ENCODER_OBJECT_ID_NUTMEG 0x22
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/* Kaleidoscope (KLDSCP) Class Display Hardware (internal) */
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#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 0x13
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#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 0x14
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@ -108,6 +113,7 @@
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#define CONNECTOR_OBJECT_ID_DISPLAYPORT 0x13
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#define CONNECTOR_OBJECT_ID_eDP 0x14
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#define CONNECTOR_OBJECT_ID_MXM 0x15
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#define CONNECTOR_OBJECT_ID_LVDS_eDP 0x16
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/* deleted */
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@ -124,6 +130,7 @@
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#define GENERIC_OBJECT_ID_GLSYNC 0x01
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#define GENERIC_OBJECT_ID_PX2_NON_DRIVABLE 0x02
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#define GENERIC_OBJECT_ID_MXM_OPM 0x03
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#define GENERIC_OBJECT_ID_STEREO_PIN 0x04 //This object could show up from Misc Object table, it follows ATOM_OBJECT format, and contains one ATOM_OBJECT_GPIO_CNTL_RECORD for the stereo pin
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/****************************************************/
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/* Graphics Object ENUM ID Definition */
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@ -360,6 +367,26 @@
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO << OBJECT_ID_SHIFT)
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#define ENCODER_ALMOND_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_ALMOND << OBJECT_ID_SHIFT)
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#define ENCODER_ALMOND_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_ALMOND << OBJECT_ID_SHIFT)
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#define ENCODER_TRAVIS_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_TRAVIS << OBJECT_ID_SHIFT)
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#define ENCODER_TRAVIS_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_TRAVIS << OBJECT_ID_SHIFT)
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#define ENCODER_NUTMEG_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_NUTMEG << OBJECT_ID_SHIFT)
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/****************************************************/
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/* Connector Object ID definition - Shared with BIOS */
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/****************************************************/
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@ -421,6 +448,14 @@
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GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
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CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
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#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID3 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
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CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
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#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID4 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\
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CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
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#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
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@ -512,6 +547,7 @@
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#define CONNECTOR_7PIN_DIN_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT)
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#define CONNECTOR_7PIN_DIN_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
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CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT)
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@ -593,6 +629,14 @@
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GRAPH_OBJECT_ENUM_ID7 << ENUM_ID_SHIFT |\
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CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_DAC
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#define CONNECTOR_LVDS_eDP_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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CONNECTOR_OBJECT_ID_LVDS_eDP << OBJECT_ID_SHIFT)
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#define CONNECTOR_LVDS_eDP_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
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CONNECTOR_OBJECT_ID_LVDS_eDP << OBJECT_ID_SHIFT)
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/****************************************************/
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/* Router Object ID definition - Shared with BIOS */
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/****************************************************/
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@ -621,6 +665,10 @@
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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GENERIC_OBJECT_ID_MXM_OPM << OBJECT_ID_SHIFT)
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#define GENERICOBJECT_STEREO_PIN_ENUM_ID1 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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GENERIC_OBJECT_ID_STEREO_PIN << OBJECT_ID_SHIFT)
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/****************************************************/
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/* Object Cap definition - Shared with BIOS */
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/****************************************************/
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File diff suppressed because it is too large
Load Diff
@ -112,6 +112,14 @@ u32 evergreen_get_temp(struct radeon_device *rdev)
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return actual_temp * 1000;
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}
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u32 sumo_get_temp(struct radeon_device *rdev)
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{
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u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
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u32 actual_temp = (temp >> 1) & 0xff;
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return actual_temp * 1000;
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}
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void evergreen_pm_misc(struct radeon_device *rdev)
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{
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int req_ps_idx = rdev->pm.requested_power_state_index;
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@ -943,31 +951,39 @@ static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_sa
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save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
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save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
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save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
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save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
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save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
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save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
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save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
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if (!(rdev->flags & RADEON_IS_IGP)) {
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save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
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save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
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save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
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save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
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}
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/* Stop all video */
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WREG32(VGA_RENDER_CONTROL, 0);
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
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if (!(rdev->flags & RADEON_IS_IGP)) {
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
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}
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WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
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WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
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WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
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WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
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WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
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WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
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if (!(rdev->flags & RADEON_IS_IGP)) {
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WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
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WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
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WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
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WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
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}
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
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if (!(rdev->flags & RADEON_IS_IGP)) {
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
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}
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WREG32(D1VGA_CONTROL, 0);
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WREG32(D2VGA_CONTROL, 0);
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@ -997,41 +1013,43 @@ static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_
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WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
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(u32)rdev->mc.vram_start);
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WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
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upper_32_bits(rdev->mc.vram_start));
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WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
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upper_32_bits(rdev->mc.vram_start));
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WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
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(u32)rdev->mc.vram_start);
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WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
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(u32)rdev->mc.vram_start);
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if (!(rdev->flags & RADEON_IS_IGP)) {
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WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
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upper_32_bits(rdev->mc.vram_start));
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WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
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upper_32_bits(rdev->mc.vram_start));
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WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
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(u32)rdev->mc.vram_start);
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WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
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(u32)rdev->mc.vram_start);
|
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|
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WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
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upper_32_bits(rdev->mc.vram_start));
|
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WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
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upper_32_bits(rdev->mc.vram_start));
|
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WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
|
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(u32)rdev->mc.vram_start);
|
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WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
|
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(u32)rdev->mc.vram_start);
|
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WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
|
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upper_32_bits(rdev->mc.vram_start));
|
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WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
|
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upper_32_bits(rdev->mc.vram_start));
|
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WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
|
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(u32)rdev->mc.vram_start);
|
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WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
|
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(u32)rdev->mc.vram_start);
|
||||
|
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WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
|
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upper_32_bits(rdev->mc.vram_start));
|
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WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
|
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upper_32_bits(rdev->mc.vram_start));
|
||||
WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
|
||||
(u32)rdev->mc.vram_start);
|
||||
WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
|
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(u32)rdev->mc.vram_start);
|
||||
WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
|
||||
upper_32_bits(rdev->mc.vram_start));
|
||||
WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
|
||||
upper_32_bits(rdev->mc.vram_start));
|
||||
WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
|
||||
(u32)rdev->mc.vram_start);
|
||||
WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
|
||||
(u32)rdev->mc.vram_start);
|
||||
|
||||
WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
|
||||
upper_32_bits(rdev->mc.vram_start));
|
||||
WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
|
||||
upper_32_bits(rdev->mc.vram_start));
|
||||
WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
|
||||
(u32)rdev->mc.vram_start);
|
||||
WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
|
||||
(u32)rdev->mc.vram_start);
|
||||
WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
|
||||
upper_32_bits(rdev->mc.vram_start));
|
||||
WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
|
||||
upper_32_bits(rdev->mc.vram_start));
|
||||
WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
|
||||
(u32)rdev->mc.vram_start);
|
||||
WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
|
||||
(u32)rdev->mc.vram_start);
|
||||
}
|
||||
|
||||
WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
|
||||
WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
|
||||
@ -1047,22 +1065,28 @@ static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_
|
||||
WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
|
||||
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
|
||||
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
|
||||
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
|
||||
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
|
||||
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
|
||||
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
|
||||
if (!(rdev->flags & RADEON_IS_IGP)) {
|
||||
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
|
||||
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
|
||||
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
|
||||
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
|
||||
}
|
||||
WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
|
||||
WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
|
||||
WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
|
||||
WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
|
||||
WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
|
||||
WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
|
||||
if (!(rdev->flags & RADEON_IS_IGP)) {
|
||||
WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
|
||||
WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
|
||||
WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
|
||||
WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
|
||||
}
|
||||
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
|
||||
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
|
||||
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
|
||||
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
|
||||
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
|
||||
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
|
||||
if (!(rdev->flags & RADEON_IS_IGP)) {
|
||||
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
|
||||
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
|
||||
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
|
||||
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
|
||||
}
|
||||
WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
|
||||
}
|
||||
|
||||
@ -1338,6 +1362,7 @@ static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
|
||||
switch (rdev->family) {
|
||||
case CHIP_CEDAR:
|
||||
case CHIP_REDWOOD:
|
||||
case CHIP_PALM:
|
||||
force_no_swizzle = false;
|
||||
break;
|
||||
case CHIP_CYPRESS:
|
||||
@ -1437,6 +1462,43 @@ static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
|
||||
return backend_map;
|
||||
}
|
||||
|
||||
static void evergreen_program_channel_remap(struct radeon_device *rdev)
|
||||
{
|
||||
u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
|
||||
|
||||
tmp = RREG32(MC_SHARED_CHMAP);
|
||||
switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
|
||||
case 0:
|
||||
case 1:
|
||||
case 2:
|
||||
case 3:
|
||||
default:
|
||||
/* default mapping */
|
||||
mc_shared_chremap = 0x00fac688;
|
||||
break;
|
||||
}
|
||||
|
||||
switch (rdev->family) {
|
||||
case CHIP_HEMLOCK:
|
||||
case CHIP_CYPRESS:
|
||||
tcp_chan_steer_lo = 0x54763210;
|
||||
tcp_chan_steer_hi = 0x0000ba98;
|
||||
break;
|
||||
case CHIP_JUNIPER:
|
||||
case CHIP_REDWOOD:
|
||||
case CHIP_CEDAR:
|
||||
case CHIP_PALM:
|
||||
default:
|
||||
tcp_chan_steer_lo = 0x76543210;
|
||||
tcp_chan_steer_hi = 0x0000ba98;
|
||||
break;
|
||||
}
|
||||
|
||||
WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
|
||||
WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
|
||||
WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
|
||||
}
|
||||
|
||||
static void evergreen_gpu_init(struct radeon_device *rdev)
|
||||
{
|
||||
u32 cc_rb_backend_disable = 0;
|
||||
@ -1544,6 +1606,27 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
|
||||
rdev->config.evergreen.max_hw_contexts = 4;
|
||||
rdev->config.evergreen.sq_num_cf_insts = 1;
|
||||
|
||||
rdev->config.evergreen.sc_prim_fifo_size = 0x40;
|
||||
rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
|
||||
rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
|
||||
break;
|
||||
case CHIP_PALM:
|
||||
rdev->config.evergreen.num_ses = 1;
|
||||
rdev->config.evergreen.max_pipes = 2;
|
||||
rdev->config.evergreen.max_tile_pipes = 2;
|
||||
rdev->config.evergreen.max_simds = 2;
|
||||
rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
|
||||
rdev->config.evergreen.max_gprs = 256;
|
||||
rdev->config.evergreen.max_threads = 192;
|
||||
rdev->config.evergreen.max_gs_threads = 16;
|
||||
rdev->config.evergreen.max_stack_entries = 256;
|
||||
rdev->config.evergreen.sx_num_of_sets = 4;
|
||||
rdev->config.evergreen.sx_max_export_size = 128;
|
||||
rdev->config.evergreen.sx_max_export_pos_size = 32;
|
||||
rdev->config.evergreen.sx_max_export_smx_size = 96;
|
||||
rdev->config.evergreen.max_hw_contexts = 4;
|
||||
rdev->config.evergreen.sq_num_cf_insts = 1;
|
||||
|
||||
rdev->config.evergreen.sc_prim_fifo_size = 0x40;
|
||||
rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
|
||||
rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
|
||||
@ -1740,6 +1823,8 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
|
||||
WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
|
||||
WREG32(HDP_ADDR_CONFIG, gb_addr_config);
|
||||
|
||||
evergreen_program_channel_remap(rdev);
|
||||
|
||||
num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
|
||||
grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
|
||||
|
||||
@ -1822,9 +1907,15 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
|
||||
GS_PRIO(2) |
|
||||
ES_PRIO(3));
|
||||
|
||||
if (rdev->family == CHIP_CEDAR)
|
||||
switch (rdev->family) {
|
||||
case CHIP_CEDAR:
|
||||
case CHIP_PALM:
|
||||
/* no vertex cache */
|
||||
sq_config &= ~VC_ENABLE;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
|
||||
|
||||
@ -1836,10 +1927,15 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
|
||||
sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
|
||||
sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
|
||||
|
||||
if (rdev->family == CHIP_CEDAR)
|
||||
switch (rdev->family) {
|
||||
case CHIP_CEDAR:
|
||||
case CHIP_PALM:
|
||||
ps_thread_count = 96;
|
||||
else
|
||||
break;
|
||||
default:
|
||||
ps_thread_count = 128;
|
||||
break;
|
||||
}
|
||||
|
||||
sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
|
||||
sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
|
||||
@ -1870,10 +1966,15 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
|
||||
WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
|
||||
FORCE_EOV_MAX_REZ_CNT(255)));
|
||||
|
||||
if (rdev->family == CHIP_CEDAR)
|
||||
switch (rdev->family) {
|
||||
case CHIP_CEDAR:
|
||||
case CHIP_PALM:
|
||||
vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
|
||||
else
|
||||
break;
|
||||
default:
|
||||
vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
|
||||
break;
|
||||
}
|
||||
vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
|
||||
WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
|
||||
|
||||
@ -1957,12 +2058,18 @@ int evergreen_mc_init(struct radeon_device *rdev)
|
||||
rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
|
||||
rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
|
||||
/* Setup GPU memory space */
|
||||
/* size in MB on evergreen */
|
||||
rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
|
||||
rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
|
||||
if (rdev->flags & RADEON_IS_IGP) {
|
||||
/* size in bytes on fusion */
|
||||
rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
|
||||
rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
|
||||
} else {
|
||||
/* size in MB on evergreen */
|
||||
rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
|
||||
rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
|
||||
}
|
||||
rdev->mc.visible_vram_size = rdev->mc.aper_size;
|
||||
rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
|
||||
r600_vram_gtt_location(rdev, &rdev->mc);
|
||||
r700_vram_gtt_location(rdev, &rdev->mc);
|
||||
radeon_update_bandwidth_info(rdev);
|
||||
|
||||
return 0;
|
||||
@ -2079,17 +2186,21 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev)
|
||||
WREG32(GRBM_INT_CNTL, 0);
|
||||
WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
|
||||
WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
|
||||
WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
|
||||
WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
|
||||
WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
|
||||
WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
|
||||
if (!(rdev->flags & RADEON_IS_IGP)) {
|
||||
WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
|
||||
WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
|
||||
WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
|
||||
WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
|
||||
}
|
||||
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
|
||||
if (!(rdev->flags & RADEON_IS_IGP)) {
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
|
||||
}
|
||||
|
||||
WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
|
||||
WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
|
||||
@ -2205,10 +2316,12 @@ int evergreen_irq_set(struct radeon_device *rdev)
|
||||
|
||||
WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
|
||||
WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
|
||||
WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
|
||||
WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
|
||||
WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
|
||||
WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
|
||||
if (!(rdev->flags & RADEON_IS_IGP)) {
|
||||
WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
|
||||
WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
|
||||
WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
|
||||
WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
|
||||
}
|
||||
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
|
||||
@ -2765,12 +2878,16 @@ static bool evergreen_card_posted(struct radeon_device *rdev)
|
||||
u32 reg;
|
||||
|
||||
/* first check CRTCs */
|
||||
reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
|
||||
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
|
||||
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
|
||||
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
|
||||
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
|
||||
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
|
||||
if (rdev->flags & RADEON_IS_IGP)
|
||||
reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
|
||||
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
|
||||
else
|
||||
reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
|
||||
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
|
||||
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
|
||||
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
|
||||
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
|
||||
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
|
||||
if (reg & EVERGREEN_CRTC_MASTER_EN)
|
||||
return true;
|
||||
|
||||
|
||||
@ -147,7 +147,8 @@ set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
|
||||
radeon_ring_write(rdev, 0);
|
||||
radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30);
|
||||
|
||||
if (rdev->family == CHIP_CEDAR)
|
||||
if ((rdev->family == CHIP_CEDAR) ||
|
||||
(rdev->family == CHIP_PALM))
|
||||
cp_set_surface_sync(rdev,
|
||||
PACKET3_TC_ACTION_ENA, 48, gpu_addr);
|
||||
else
|
||||
@ -331,9 +332,31 @@ set_default_state(struct radeon_device *rdev)
|
||||
num_hs_stack_entries = 85;
|
||||
num_ls_stack_entries = 85;
|
||||
break;
|
||||
case CHIP_PALM:
|
||||
num_ps_gprs = 93;
|
||||
num_vs_gprs = 46;
|
||||
num_temp_gprs = 4;
|
||||
num_gs_gprs = 31;
|
||||
num_es_gprs = 31;
|
||||
num_hs_gprs = 23;
|
||||
num_ls_gprs = 23;
|
||||
num_ps_threads = 96;
|
||||
num_vs_threads = 16;
|
||||
num_gs_threads = 16;
|
||||
num_es_threads = 16;
|
||||
num_hs_threads = 16;
|
||||
num_ls_threads = 16;
|
||||
num_ps_stack_entries = 42;
|
||||
num_vs_stack_entries = 42;
|
||||
num_gs_stack_entries = 42;
|
||||
num_es_stack_entries = 42;
|
||||
num_hs_stack_entries = 42;
|
||||
num_ls_stack_entries = 42;
|
||||
break;
|
||||
}
|
||||
|
||||
if (rdev->family == CHIP_CEDAR)
|
||||
if ((rdev->family == CHIP_CEDAR) ||
|
||||
(rdev->family == CHIP_PALM))
|
||||
sq_config = 0;
|
||||
else
|
||||
sq_config = VC_ENABLE;
|
||||
|
||||
@ -164,11 +164,13 @@
|
||||
#define SE_SC_BUSY (1 << 29)
|
||||
#define SE_DB_BUSY (1 << 30)
|
||||
#define SE_CB_BUSY (1 << 31)
|
||||
|
||||
/* evergreen */
|
||||
#define CG_MULT_THERMAL_STATUS 0x740
|
||||
#define ASIC_T(x) ((x) << 16)
|
||||
#define ASIC_T_MASK 0x7FF0000
|
||||
#define ASIC_T_SHIFT 16
|
||||
/* APU */
|
||||
#define CG_THERMAL_STATUS 0x678
|
||||
|
||||
#define HDP_HOST_PATH_CNTL 0x2C00
|
||||
#define HDP_NONSURFACE_BASE 0x2C04
|
||||
@ -180,6 +182,7 @@
|
||||
#define MC_SHARED_CHMAP 0x2004
|
||||
#define NOOFCHAN_SHIFT 12
|
||||
#define NOOFCHAN_MASK 0x00003000
|
||||
#define MC_SHARED_CHREMAP 0x2008
|
||||
|
||||
#define MC_ARB_RAMCFG 0x2760
|
||||
#define NOOFBANK_SHIFT 0
|
||||
@ -348,6 +351,9 @@
|
||||
#define SYNC_WALKER (1 << 25)
|
||||
#define SYNC_ALIGNER (1 << 26)
|
||||
|
||||
#define TCP_CHAN_STEER_LO 0x960c
|
||||
#define TCP_CHAN_STEER_HI 0x9610
|
||||
|
||||
#define VGT_CACHE_INVALIDATION 0x88C4
|
||||
#define CACHE_INVALIDATION(x) ((x) << 0)
|
||||
#define VC_ONLY 0
|
||||
|
||||
@ -83,6 +83,9 @@ MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
|
||||
MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
|
||||
MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
|
||||
MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
|
||||
MODULE_FIRMWARE("radeon/PALM_pfp.bin");
|
||||
MODULE_FIRMWARE("radeon/PALM_me.bin");
|
||||
MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
|
||||
|
||||
int r600_debugfs_mc_info_init(struct radeon_device *rdev);
|
||||
|
||||
@ -1161,7 +1164,7 @@ static void r600_mc_program(struct radeon_device *rdev)
|
||||
* Note: GTT start, end, size should be initialized before calling this
|
||||
* function on AGP platform.
|
||||
*/
|
||||
void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
|
||||
static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
|
||||
{
|
||||
u64 size_bf, size_af;
|
||||
|
||||
@ -1998,6 +2001,10 @@ int r600_init_microcode(struct radeon_device *rdev)
|
||||
chip_name = "CYPRESS";
|
||||
rlc_chip_name = "CYPRESS";
|
||||
break;
|
||||
case CHIP_PALM:
|
||||
chip_name = "PALM";
|
||||
rlc_chip_name = "SUMO";
|
||||
break;
|
||||
default: BUG();
|
||||
}
|
||||
|
||||
|
||||
@ -181,6 +181,7 @@ void rs690_pm_info(struct radeon_device *rdev);
|
||||
extern u32 rv6xx_get_temp(struct radeon_device *rdev);
|
||||
extern u32 rv770_get_temp(struct radeon_device *rdev);
|
||||
extern u32 evergreen_get_temp(struct radeon_device *rdev);
|
||||
extern u32 sumo_get_temp(struct radeon_device *rdev);
|
||||
|
||||
/*
|
||||
* Fences.
|
||||
@ -737,6 +738,7 @@ enum radeon_int_thermal_type {
|
||||
THERMAL_TYPE_RV6XX,
|
||||
THERMAL_TYPE_RV770,
|
||||
THERMAL_TYPE_EVERGREEN,
|
||||
THERMAL_TYPE_SUMO,
|
||||
};
|
||||
|
||||
struct radeon_voltage {
|
||||
@ -1323,6 +1325,7 @@ void r100_pll_errata_after_index(struct radeon_device *rdev);
|
||||
#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
|
||||
#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
|
||||
#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
|
||||
#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM))
|
||||
|
||||
/*
|
||||
* BIOS helpers.
|
||||
@ -1489,7 +1492,6 @@ extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
|
||||
struct drm_display_mode *mode2);
|
||||
|
||||
/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
|
||||
extern void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
|
||||
extern bool r600_card_posted(struct radeon_device *rdev);
|
||||
extern void r600_cp_stop(struct radeon_device *rdev);
|
||||
extern int r600_cp_start(struct radeon_device *rdev);
|
||||
@ -1535,6 +1537,7 @@ extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mo
|
||||
extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
|
||||
extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
|
||||
|
||||
extern void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
|
||||
extern void r700_cp_stop(struct radeon_device *rdev);
|
||||
extern void r700_cp_fini(struct radeon_device *rdev);
|
||||
extern void evergreen_disable_interrupt_state(struct radeon_device *rdev);
|
||||
|
||||
@ -793,6 +793,49 @@ static struct radeon_asic evergreen_asic = {
|
||||
.post_page_flip = &evergreen_post_page_flip,
|
||||
};
|
||||
|
||||
static struct radeon_asic sumo_asic = {
|
||||
.init = &evergreen_init,
|
||||
.fini = &evergreen_fini,
|
||||
.suspend = &evergreen_suspend,
|
||||
.resume = &evergreen_resume,
|
||||
.cp_commit = &r600_cp_commit,
|
||||
.gpu_is_lockup = &evergreen_gpu_is_lockup,
|
||||
.asic_reset = &evergreen_asic_reset,
|
||||
.vga_set_state = &r600_vga_set_state,
|
||||
.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
|
||||
.gart_set_page = &rs600_gart_set_page,
|
||||
.ring_test = &r600_ring_test,
|
||||
.ring_ib_execute = &r600_ring_ib_execute,
|
||||
.irq_set = &evergreen_irq_set,
|
||||
.irq_process = &evergreen_irq_process,
|
||||
.get_vblank_counter = &evergreen_get_vblank_counter,
|
||||
.fence_ring_emit = &r600_fence_ring_emit,
|
||||
.cs_parse = &evergreen_cs_parse,
|
||||
.copy_blit = &evergreen_copy_blit,
|
||||
.copy_dma = &evergreen_copy_blit,
|
||||
.copy = &evergreen_copy_blit,
|
||||
.get_engine_clock = &radeon_atom_get_engine_clock,
|
||||
.set_engine_clock = &radeon_atom_set_engine_clock,
|
||||
.get_memory_clock = NULL,
|
||||
.set_memory_clock = NULL,
|
||||
.get_pcie_lanes = NULL,
|
||||
.set_pcie_lanes = NULL,
|
||||
.set_clock_gating = NULL,
|
||||
.set_surface_reg = r600_set_surface_reg,
|
||||
.clear_surface_reg = r600_clear_surface_reg,
|
||||
.bandwidth_update = &evergreen_bandwidth_update,
|
||||
.hpd_init = &evergreen_hpd_init,
|
||||
.hpd_fini = &evergreen_hpd_fini,
|
||||
.hpd_sense = &evergreen_hpd_sense,
|
||||
.hpd_set_polarity = &evergreen_hpd_set_polarity,
|
||||
.gui_idle = &r600_gui_idle,
|
||||
.pm_misc = &evergreen_pm_misc,
|
||||
.pm_prepare = &evergreen_pm_prepare,
|
||||
.pm_finish = &evergreen_pm_finish,
|
||||
.pm_init_profile = &rs780_pm_init_profile,
|
||||
.pm_get_dynpm_state = &r600_pm_get_dynpm_state,
|
||||
};
|
||||
|
||||
int radeon_asic_init(struct radeon_device *rdev)
|
||||
{
|
||||
radeon_register_accessor_init(rdev);
|
||||
@ -877,6 +920,9 @@ int radeon_asic_init(struct radeon_device *rdev)
|
||||
case CHIP_HEMLOCK:
|
||||
rdev->asic = &evergreen_asic;
|
||||
break;
|
||||
case CHIP_PALM:
|
||||
rdev->asic = &sumo_asic;
|
||||
break;
|
||||
default:
|
||||
/* FIXME: not supported yet */
|
||||
return -EINVAL;
|
||||
@ -891,7 +937,9 @@ int radeon_asic_init(struct radeon_device *rdev)
|
||||
if (rdev->flags & RADEON_SINGLE_CRTC)
|
||||
rdev->num_crtc = 1;
|
||||
else {
|
||||
if (ASIC_IS_DCE4(rdev))
|
||||
if (ASIC_IS_DCE41(rdev))
|
||||
rdev->num_crtc = 2;
|
||||
else if (ASIC_IS_DCE4(rdev))
|
||||
rdev->num_crtc = 6;
|
||||
else
|
||||
rdev->num_crtc = 2;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -335,7 +335,12 @@ bool radeon_card_posted(struct radeon_device *rdev)
|
||||
uint32_t reg;
|
||||
|
||||
/* first check CRTCs */
|
||||
if (ASIC_IS_DCE4(rdev)) {
|
||||
if (ASIC_IS_DCE41(rdev)) {
|
||||
reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
|
||||
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
|
||||
if (reg & EVERGREEN_CRTC_MASTER_EN)
|
||||
return true;
|
||||
} else if (ASIC_IS_DCE4(rdev)) {
|
||||
reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
|
||||
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
|
||||
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
|
||||
|
||||
@ -485,7 +485,7 @@ static void radeon_crtc_init(struct drm_device *dev, int index)
|
||||
radeon_legacy_init_crtc(dev, radeon_crtc);
|
||||
}
|
||||
|
||||
static const char *encoder_names[34] = {
|
||||
static const char *encoder_names[36] = {
|
||||
"NONE",
|
||||
"INTERNAL_LVDS",
|
||||
"INTERNAL_TMDS1",
|
||||
@ -520,6 +520,8 @@ static const char *encoder_names[34] = {
|
||||
"INTERNAL_KLDSCP_LVTMA",
|
||||
"INTERNAL_UNIPHY1",
|
||||
"INTERNAL_UNIPHY2",
|
||||
"NUTMEG",
|
||||
"TRAVIS",
|
||||
};
|
||||
|
||||
static const char *connector_names[15] = {
|
||||
|
||||
@ -713,7 +713,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
|
||||
* DIG1/2 can drive UNIPHY0/1/2 link A or link B
|
||||
*
|
||||
* DCE 4.0
|
||||
* - 3 DIG transmitter blocks UNPHY0/1/2 (links A and B).
|
||||
* - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
|
||||
* Supports up to 6 digital outputs
|
||||
* - 6 DIG encoder blocks.
|
||||
* - DIG to PHY mapping is hardcoded
|
||||
@ -724,6 +724,12 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
|
||||
* DIG5 drives UNIPHY2 link A, A+B
|
||||
* DIG6 drives UNIPHY2 link B
|
||||
*
|
||||
* DCE 4.1
|
||||
* - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
|
||||
* Supports up to 6 digital outputs
|
||||
* - 2 DIG encoder blocks.
|
||||
* DIG1/2 can drive UNIPHY0/1/2 link A or link B
|
||||
*
|
||||
* Routing
|
||||
* crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
|
||||
* Examples:
|
||||
@ -904,9 +910,15 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
|
||||
else
|
||||
args.v3.ucLaneNum = 4;
|
||||
|
||||
if (dig->linkb) {
|
||||
args.v3.acConfig.ucLinkSel = 1;
|
||||
args.v3.acConfig.ucEncoderSel = 1;
|
||||
if (ASIC_IS_DCE41(rdev)) {
|
||||
args.v3.acConfig.ucEncoderSel = dig->dig_encoder;
|
||||
if (dig->linkb)
|
||||
args.v3.acConfig.ucLinkSel = 1;
|
||||
} else {
|
||||
if (dig->linkb) {
|
||||
args.v3.acConfig.ucLinkSel = 1;
|
||||
args.v3.acConfig.ucEncoderSel = 1;
|
||||
}
|
||||
}
|
||||
|
||||
/* Select the PLL for the PHY
|
||||
@ -1044,6 +1056,7 @@ atombios_set_edp_panel_power(struct drm_connector *connector, int action)
|
||||
|
||||
union external_encoder_control {
|
||||
EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
|
||||
EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
|
||||
};
|
||||
|
||||
static void
|
||||
@ -1054,6 +1067,7 @@ atombios_external_encoder_setup(struct drm_encoder *encoder,
|
||||
struct drm_device *dev = encoder->dev;
|
||||
struct radeon_device *rdev = dev->dev_private;
|
||||
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
|
||||
struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
|
||||
union external_encoder_control args;
|
||||
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
|
||||
int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
|
||||
@ -1061,6 +1075,7 @@ atombios_external_encoder_setup(struct drm_encoder *encoder,
|
||||
int dp_clock = 0;
|
||||
int dp_lane_count = 0;
|
||||
int connector_object_id = 0;
|
||||
u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
|
||||
|
||||
if (connector) {
|
||||
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
|
||||
@ -1099,6 +1114,37 @@ atombios_external_encoder_setup(struct drm_encoder *encoder,
|
||||
else
|
||||
args.v1.sDigEncoder.ucLaneNum = 4;
|
||||
break;
|
||||
case 3:
|
||||
args.v3.sExtEncoder.ucAction = action;
|
||||
if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
|
||||
args.v3.sExtEncoder.usConnectorId = connector_object_id;
|
||||
else
|
||||
args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
|
||||
args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
|
||||
|
||||
if (args.v3.sExtEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
|
||||
if (dp_clock == 270000)
|
||||
args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
|
||||
else if (dp_clock == 540000)
|
||||
args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
|
||||
args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
|
||||
} else if (radeon_encoder->pixel_clock > 165000)
|
||||
args.v3.sExtEncoder.ucLaneNum = 8;
|
||||
else
|
||||
args.v3.sExtEncoder.ucLaneNum = 4;
|
||||
switch (ext_enum) {
|
||||
case GRAPH_OBJECT_ENUM_ID1:
|
||||
args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
|
||||
break;
|
||||
case GRAPH_OBJECT_ENUM_ID2:
|
||||
args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
|
||||
break;
|
||||
case GRAPH_OBJECT_ENUM_ID3:
|
||||
args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
|
||||
break;
|
||||
}
|
||||
args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
|
||||
break;
|
||||
default:
|
||||
DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
|
||||
return;
|
||||
@ -1289,12 +1335,18 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
|
||||
switch (mode) {
|
||||
case DRM_MODE_DPMS_ON:
|
||||
default:
|
||||
action = ATOM_ENABLE;
|
||||
if (ASIC_IS_DCE41(rdev) && (rdev->flags & RADEON_IS_IGP))
|
||||
action = EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT;
|
||||
else
|
||||
action = ATOM_ENABLE;
|
||||
break;
|
||||
case DRM_MODE_DPMS_STANDBY:
|
||||
case DRM_MODE_DPMS_SUSPEND:
|
||||
case DRM_MODE_DPMS_OFF:
|
||||
action = ATOM_DISABLE;
|
||||
if (ASIC_IS_DCE41(rdev) && (rdev->flags & RADEON_IS_IGP))
|
||||
action = EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT;
|
||||
else
|
||||
action = ATOM_DISABLE;
|
||||
break;
|
||||
}
|
||||
atombios_external_encoder_setup(encoder, ext_encoder, action);
|
||||
@ -1483,6 +1535,11 @@ static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
|
||||
struct radeon_encoder_atom_dig *dig;
|
||||
uint32_t dig_enc_in_use = 0;
|
||||
|
||||
/* on DCE41 and encoder can driver any phy so just crtc id */
|
||||
if (ASIC_IS_DCE41(rdev)) {
|
||||
return radeon_crtc->crtc_id;
|
||||
}
|
||||
|
||||
if (ASIC_IS_DCE4(rdev)) {
|
||||
dig = radeon_encoder->enc_priv;
|
||||
switch (radeon_encoder->encoder_id) {
|
||||
@ -1610,7 +1667,13 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
|
||||
}
|
||||
|
||||
if (ext_encoder) {
|
||||
atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
|
||||
if (ASIC_IS_DCE41(rdev) && (rdev->flags & RADEON_IS_IGP)) {
|
||||
atombios_external_encoder_setup(encoder, ext_encoder,
|
||||
EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
|
||||
atombios_external_encoder_setup(encoder, ext_encoder,
|
||||
EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
|
||||
} else
|
||||
atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
|
||||
}
|
||||
|
||||
atombios_apply_encoder_quirks(encoder, adjusted_mode);
|
||||
@ -2029,6 +2092,8 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t
|
||||
case ENCODER_OBJECT_ID_TITFP513:
|
||||
case ENCODER_OBJECT_ID_VT1623:
|
||||
case ENCODER_OBJECT_ID_HDMI_SI1930:
|
||||
case ENCODER_OBJECT_ID_TRAVIS:
|
||||
case ENCODER_OBJECT_ID_NUTMEG:
|
||||
/* these are handled by the primary encoders */
|
||||
radeon_encoder->is_ext_encoder = true;
|
||||
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
|
||||
|
||||
@ -80,6 +80,7 @@ enum radeon_family {
|
||||
CHIP_JUNIPER,
|
||||
CHIP_CYPRESS,
|
||||
CHIP_HEMLOCK,
|
||||
CHIP_PALM,
|
||||
CHIP_LAST,
|
||||
};
|
||||
|
||||
|
||||
@ -125,7 +125,7 @@ int radeon_irq_kms_init(struct radeon_device *rdev)
|
||||
* chips. Disable MSI on them for now.
|
||||
*/
|
||||
if ((rdev->family >= CHIP_RV380) &&
|
||||
(!(rdev->flags & RADEON_IS_IGP)) &&
|
||||
((!(rdev->flags & RADEON_IS_IGP)) || (rdev->family >= CHIP_PALM)) &&
|
||||
(!(rdev->flags & RADEON_IS_AGP))) {
|
||||
int ret = pci_enable_msi(rdev->pdev);
|
||||
if (!ret) {
|
||||
|
||||
@ -449,6 +449,9 @@ static ssize_t radeon_hwmon_show_temp(struct device *dev,
|
||||
case THERMAL_TYPE_EVERGREEN:
|
||||
temp = evergreen_get_temp(rdev);
|
||||
break;
|
||||
case THERMAL_TYPE_SUMO:
|
||||
temp = sumo_get_temp(rdev);
|
||||
break;
|
||||
default:
|
||||
temp = 0;
|
||||
break;
|
||||
@ -487,6 +490,7 @@ static int radeon_hwmon_init(struct radeon_device *rdev)
|
||||
case THERMAL_TYPE_RV6XX:
|
||||
case THERMAL_TYPE_RV770:
|
||||
case THERMAL_TYPE_EVERGREEN:
|
||||
case THERMAL_TYPE_SUMO:
|
||||
rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
|
||||
if (IS_ERR(rdev->pm.int_hwmon_dev)) {
|
||||
err = PTR_ERR(rdev->pm.int_hwmon_dev);
|
||||
|
||||
@ -271,6 +271,12 @@ static void rv770_mc_program(struct radeon_device *rdev)
|
||||
rdev->mc.vram_end >> 12);
|
||||
}
|
||||
WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
|
||||
if (rdev->flags & RADEON_IS_IGP) {
|
||||
tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
|
||||
tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
|
||||
tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
|
||||
WREG32(MC_FUS_VM_FB_OFFSET, tmp);
|
||||
}
|
||||
tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
|
||||
tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
|
||||
WREG32(MC_VM_FB_LOCATION, tmp);
|
||||
@ -523,6 +529,49 @@ static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
|
||||
return backend_map;
|
||||
}
|
||||
|
||||
static void rv770_program_channel_remap(struct radeon_device *rdev)
|
||||
{
|
||||
u32 tcp_chan_steer, mc_shared_chremap, tmp;
|
||||
bool force_no_swizzle;
|
||||
|
||||
switch (rdev->family) {
|
||||
case CHIP_RV770:
|
||||
case CHIP_RV730:
|
||||
force_no_swizzle = false;
|
||||
break;
|
||||
case CHIP_RV710:
|
||||
case CHIP_RV740:
|
||||
default:
|
||||
force_no_swizzle = true;
|
||||
break;
|
||||
}
|
||||
|
||||
tmp = RREG32(MC_SHARED_CHMAP);
|
||||
switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
|
||||
case 0:
|
||||
case 1:
|
||||
default:
|
||||
/* default mapping */
|
||||
mc_shared_chremap = 0x00fac688;
|
||||
break;
|
||||
case 2:
|
||||
case 3:
|
||||
if (force_no_swizzle)
|
||||
mc_shared_chremap = 0x00fac688;
|
||||
else
|
||||
mc_shared_chremap = 0x00bbc298;
|
||||
break;
|
||||
}
|
||||
|
||||
if (rdev->family == CHIP_RV740)
|
||||
tcp_chan_steer = 0x00ef2a60;
|
||||
else
|
||||
tcp_chan_steer = 0x00fac688;
|
||||
|
||||
WREG32(TCP_CHAN_STEER, tcp_chan_steer);
|
||||
WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
|
||||
}
|
||||
|
||||
static void rv770_gpu_init(struct radeon_device *rdev)
|
||||
{
|
||||
int i, j, num_qd_pipes;
|
||||
@ -722,6 +771,8 @@ static void rv770_gpu_init(struct radeon_device *rdev)
|
||||
WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
|
||||
WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
|
||||
|
||||
rv770_program_channel_remap(rdev);
|
||||
|
||||
WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
|
||||
WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
|
||||
WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
|
||||
@ -990,6 +1041,50 @@ static void rv770_vram_scratch_fini(struct radeon_device *rdev)
|
||||
radeon_bo_unref(&rdev->vram_scratch.robj);
|
||||
}
|
||||
|
||||
void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
|
||||
{
|
||||
u64 size_bf, size_af;
|
||||
|
||||
if (mc->mc_vram_size > 0xE0000000) {
|
||||
/* leave room for at least 512M GTT */
|
||||
dev_warn(rdev->dev, "limiting VRAM\n");
|
||||
mc->real_vram_size = 0xE0000000;
|
||||
mc->mc_vram_size = 0xE0000000;
|
||||
}
|
||||
if (rdev->flags & RADEON_IS_AGP) {
|
||||
size_bf = mc->gtt_start;
|
||||
size_af = 0xFFFFFFFF - mc->gtt_end + 1;
|
||||
if (size_bf > size_af) {
|
||||
if (mc->mc_vram_size > size_bf) {
|
||||
dev_warn(rdev->dev, "limiting VRAM\n");
|
||||
mc->real_vram_size = size_bf;
|
||||
mc->mc_vram_size = size_bf;
|
||||
}
|
||||
mc->vram_start = mc->gtt_start - mc->mc_vram_size;
|
||||
} else {
|
||||
if (mc->mc_vram_size > size_af) {
|
||||
dev_warn(rdev->dev, "limiting VRAM\n");
|
||||
mc->real_vram_size = size_af;
|
||||
mc->mc_vram_size = size_af;
|
||||
}
|
||||
mc->vram_start = mc->gtt_end;
|
||||
}
|
||||
mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
|
||||
dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
|
||||
mc->mc_vram_size >> 20, mc->vram_start,
|
||||
mc->vram_end, mc->real_vram_size >> 20);
|
||||
} else {
|
||||
u64 base = 0;
|
||||
if (rdev->flags & RADEON_IS_IGP) {
|
||||
base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
|
||||
base |= RREG32(MC_FUS_VM_FB_OFFSET) & 0x00F00000;
|
||||
}
|
||||
radeon_vram_location(rdev, &rdev->mc, base);
|
||||
rdev->mc.gtt_base_align = 0;
|
||||
radeon_gtt_location(rdev, mc);
|
||||
}
|
||||
}
|
||||
|
||||
int rv770_mc_init(struct radeon_device *rdev)
|
||||
{
|
||||
u32 tmp;
|
||||
@ -1030,7 +1125,7 @@ int rv770_mc_init(struct radeon_device *rdev)
|
||||
rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
|
||||
rdev->mc.visible_vram_size = rdev->mc.aper_size;
|
||||
rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
|
||||
r600_vram_gtt_location(rdev, &rdev->mc);
|
||||
r700_vram_gtt_location(rdev, &rdev->mc);
|
||||
radeon_update_bandwidth_info(rdev);
|
||||
|
||||
return 0;
|
||||
|
||||
@ -138,6 +138,7 @@
|
||||
#define MC_SHARED_CHMAP 0x2004
|
||||
#define NOOFCHAN_SHIFT 12
|
||||
#define NOOFCHAN_MASK 0x00003000
|
||||
#define MC_SHARED_CHREMAP 0x2008
|
||||
|
||||
#define MC_ARB_RAMCFG 0x2760
|
||||
#define NOOFBANK_SHIFT 0
|
||||
@ -157,6 +158,7 @@
|
||||
#define MC_VM_AGP_BOT 0x202C
|
||||
#define MC_VM_AGP_BASE 0x2030
|
||||
#define MC_VM_FB_LOCATION 0x2024
|
||||
#define MC_FUS_VM_FB_OFFSET 0x2898
|
||||
#define MC_VM_MB_L1_TLB0_CNTL 0x2234
|
||||
#define MC_VM_MB_L1_TLB1_CNTL 0x2238
|
||||
#define MC_VM_MB_L1_TLB2_CNTL 0x223C
|
||||
@ -303,6 +305,7 @@
|
||||
#define BILINEAR_PRECISION_8_BIT (1 << 31)
|
||||
|
||||
#define TCP_CNTL 0x9610
|
||||
#define TCP_CHAN_STEER 0x9614
|
||||
|
||||
#define VGT_CACHE_INVALIDATION 0x88C4
|
||||
#define CACHE_INVALIDATION(x) ((x)<<0)
|
||||
|
||||
@ -419,6 +419,10 @@
|
||||
{0x1002, 0x9713, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS880|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x9714, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS880|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x9715, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS880|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x9802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PALM|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x9803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PALM|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x9804, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PALM|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PALM|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0, 0, 0}
|
||||
|
||||
#define r128_PCI_IDS \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user