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https://github.com/FEX-Emu/linux.git
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The i.MX SoC updates for 4.4:
- Enable suspend and cpufreq support for i.MX6UL - Add platform level ENET initialization support for i.MX7D -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJWJP9yAAoJEFBXWFqHsHzOJvQH/3sncCMvFmOXX1hBJzb4BzE6 4Ke4AC39v1TuviNkVZooMiVlW5uf4tvyvyv47GjF88yRsHJmvt1s0T7502v4+dib Ak6dj58uqdC4yj6RF5eZBwqHV4s3nZbESYt4Dr17rka/HqhvhH7yxFpWBzPWqLUb YK5nlyBe8r9Mrsgr8mkFEKHmzgMhOTlomkUk3f5BL7TjrRCA+b5Czed/P0hZ7OVx cIqALqMregcqmvH21bA6feSs1NARLfcBraWH4/YxSRFrXng8XCb1bGF6P8U78bSz aQ6VZFWEInJBNKfQR+5N5+yfPnm25AIAHdqv1cyIODBPbFy7t5hyyzdmtEmNskM= =naPW -----END PGP SIGNATURE----- Merge tag 'imx-soc-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc The i.MX SoC updates for 4.4: - Enable suspend and cpufreq support for i.MX6UL - Add platform level ENET initialization support for i.MX7D * tag 'imx-soc-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: imx: add cpufreq device for imx6ul ARM: imx: add enet init for i.MX7D platform ARM: imx7d: add imx7d iomux-gpr field define ARM: imx: add suspend/resume support for i.mx6ul Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
fa54cda779
@ -131,6 +131,7 @@ void imx6q_pm_init(void);
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void imx6dl_pm_init(void);
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void imx6sl_pm_init(void);
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void imx6sx_pm_init(void);
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void imx6ul_pm_init(void);
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#ifdef CONFIG_PM
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void imx51_pm_init(void);
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@ -67,6 +67,7 @@ static void __init imx6ul_init_machine(void)
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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imx6ul_enet_init();
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imx_anatop_init();
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imx6ul_pm_init();
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}
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static void __init imx6ul_init_irq(void)
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@ -74,6 +75,13 @@ static void __init imx6ul_init_irq(void)
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imx_init_revision_from_anatop();
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imx_src_init();
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irqchip_init();
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imx6_pm_ccm_init("fsl,imx6ul-ccm");
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}
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static void __init imx6ul_init_late(void)
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{
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if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
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platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
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}
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static const char *imx6ul_dt_compat[] __initconst = {
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@ -84,5 +92,6 @@ static const char *imx6ul_dt_compat[] __initconst = {
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DT_MACHINE_START(IMX6UL, "Freescale i.MX6 Ultralite (Device Tree)")
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.init_irq = imx6ul_init_irq,
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.init_machine = imx6ul_init_machine,
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.init_late = imx6ul_init_late,
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.dt_compat = imx6ul_dt_compat,
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MACHINE_END
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@ -6,12 +6,85 @@
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* published by the Free Software Foundation.
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*/
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#include <linux/irqchip.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
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#include <linux/of_platform.h>
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#include <linux/phy.h>
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#include <linux/regmap.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include "common.h"
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static int ar8031_phy_fixup(struct phy_device *dev)
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{
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u16 val;
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/* Set RGMII IO voltage to 1.8V */
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phy_write(dev, 0x1d, 0x1f);
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phy_write(dev, 0x1e, 0x8);
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/* disable phy AR8031 SmartEEE function. */
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phy_write(dev, 0xd, 0x3);
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phy_write(dev, 0xe, 0x805d);
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phy_write(dev, 0xd, 0x4003);
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val = phy_read(dev, 0xe);
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val &= ~(0x1 << 8);
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phy_write(dev, 0xe, val);
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/* introduce tx clock delay */
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phy_write(dev, 0x1d, 0x5);
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val = phy_read(dev, 0x1e);
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val |= 0x0100;
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phy_write(dev, 0x1e, val);
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return 0;
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}
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static int bcm54220_phy_fixup(struct phy_device *dev)
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{
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/* enable RXC skew select RGMII copper mode */
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phy_write(dev, 0x1e, 0x21);
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phy_write(dev, 0x1f, 0x7ea8);
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phy_write(dev, 0x1e, 0x2f);
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phy_write(dev, 0x1f, 0x71b7);
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return 0;
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}
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#define PHY_ID_AR8031 0x004dd074
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#define PHY_ID_BCM54220 0x600d8589
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static void __init imx7d_enet_phy_init(void)
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{
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if (IS_BUILTIN(CONFIG_PHYLIB)) {
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phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
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ar8031_phy_fixup);
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phy_register_fixup_for_uid(PHY_ID_BCM54220, 0xffffffff,
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bcm54220_phy_fixup);
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}
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}
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static void __init imx7d_enet_clk_sel(void)
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{
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struct regmap *gpr;
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gpr = syscon_regmap_lookup_by_compatible("fsl,imx7d-iomuxc-gpr");
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if (!IS_ERR(gpr)) {
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regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK, 0);
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regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_CLK_DIR_MASK, 0);
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} else {
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pr_err("failed to find fsl,imx7d-iomux-gpr regmap\n");
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}
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}
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static inline void imx7d_enet_init(void)
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{
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imx7d_enet_phy_init();
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imx7d_enet_clk_sel();
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}
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static void __init imx7d_init_machine(void)
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{
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struct device *parent;
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@ -22,6 +95,7 @@ static void __init imx7d_init_machine(void)
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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imx_anatop_init();
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imx7d_enet_init();
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}
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static void __init imx7d_init_irq(void)
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@ -93,6 +93,7 @@ struct imx6_pm_socdata {
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const char *src_compat;
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const char *iomuxc_compat;
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const char *gpc_compat;
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const char *pl310_compat;
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const u32 mmdc_io_num;
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const u32 *mmdc_io_offset;
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};
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@ -137,11 +138,19 @@ static const u32 imx6sx_mmdc_io_offset[] __initconst = {
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0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */
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};
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static const u32 imx6ul_mmdc_io_offset[] __initconst = {
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0x244, 0x248, 0x24c, 0x250, /* DQM0, DQM1, RAS, CAS */
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0x27c, 0x498, 0x4a4, 0x490, /* SDCLK0, GPR_B0DS-B1DS, GPR_ADDS */
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0x280, 0x284, 0x260, 0x264, /* SDQS0~1, SODT0, SODT1 */
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0x494, 0x4b0, /* MODE_CTL, MODE, */
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};
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static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
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.mmdc_compat = "fsl,imx6q-mmdc",
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.src_compat = "fsl,imx6q-src",
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.iomuxc_compat = "fsl,imx6q-iomuxc",
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.gpc_compat = "fsl,imx6q-gpc",
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.pl310_compat = "arm,pl310-cache",
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.mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_offset),
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.mmdc_io_offset = imx6q_mmdc_io_offset,
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};
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@ -151,6 +160,7 @@ static const struct imx6_pm_socdata imx6dl_pm_data __initconst = {
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.src_compat = "fsl,imx6q-src",
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.iomuxc_compat = "fsl,imx6dl-iomuxc",
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.gpc_compat = "fsl,imx6q-gpc",
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.pl310_compat = "arm,pl310-cache",
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.mmdc_io_num = ARRAY_SIZE(imx6dl_mmdc_io_offset),
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.mmdc_io_offset = imx6dl_mmdc_io_offset,
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};
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@ -160,6 +170,7 @@ static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
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.src_compat = "fsl,imx6sl-src",
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.iomuxc_compat = "fsl,imx6sl-iomuxc",
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.gpc_compat = "fsl,imx6sl-gpc",
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.pl310_compat = "arm,pl310-cache",
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.mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset),
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.mmdc_io_offset = imx6sl_mmdc_io_offset,
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};
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@ -169,10 +180,21 @@ static const struct imx6_pm_socdata imx6sx_pm_data __initconst = {
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.src_compat = "fsl,imx6sx-src",
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.iomuxc_compat = "fsl,imx6sx-iomuxc",
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.gpc_compat = "fsl,imx6sx-gpc",
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.pl310_compat = "arm,pl310-cache",
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.mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_offset),
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.mmdc_io_offset = imx6sx_mmdc_io_offset,
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};
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static const struct imx6_pm_socdata imx6ul_pm_data __initconst = {
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.mmdc_compat = "fsl,imx6ul-mmdc",
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.src_compat = "fsl,imx6ul-src",
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.iomuxc_compat = "fsl,imx6ul-iomuxc",
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.gpc_compat = "fsl,imx6ul-gpc",
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.pl310_compat = NULL,
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.mmdc_io_num = ARRAY_SIZE(imx6ul_mmdc_io_offset),
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.mmdc_io_offset = imx6ul_mmdc_io_offset,
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};
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/*
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* This structure is for passing necessary data for low level ocram
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* suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct
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@ -290,7 +312,7 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode)
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val |= BM_CLPCR_SBYOS;
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if (cpu_is_imx6sl())
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val |= BM_CLPCR_BYPASS_PMIC_READY;
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if (cpu_is_imx6sl() || cpu_is_imx6sx())
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if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul())
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val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
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else
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val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
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@ -330,6 +352,10 @@ static int imx6q_suspend_finish(unsigned long val)
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* as we need to float DDR IO.
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*/
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local_flush_tlb_all();
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/* check if need to flush internal L2 cache */
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if (!((struct imx6_cpu_pm_info *)
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suspend_ocram_base)->l2_base.vbase)
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flush_cache_all();
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imx6_suspend_in_ocram_fn(suspend_ocram_base);
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}
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@ -470,6 +496,7 @@ static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
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suspend_ocram_base = __arm_ioremap_exec(ocram_pbase,
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MX6Q_SUSPEND_OCRAM_SIZE, false);
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memset(suspend_ocram_base, 0, sizeof(*pm_info));
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pm_info = suspend_ocram_base;
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pm_info->pbase = ocram_pbase;
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pm_info->resume_addr = virt_to_phys(v7_cpu_resume);
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@ -505,11 +532,13 @@ static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
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goto gpc_map_failed;
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}
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ret = imx6_pm_get_base(&pm_info->l2_base, "arm,pl310-cache");
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if (ret) {
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pr_warn("%s: failed to get pl310-cache base %d!\n",
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__func__, ret);
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goto pl310_cache_map_failed;
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if (socdata->pl310_compat) {
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ret = imx6_pm_get_base(&pm_info->l2_base, socdata->pl310_compat);
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if (ret) {
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pr_warn("%s: failed to get pl310-cache base %d!\n",
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__func__, ret);
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goto pl310_cache_map_failed;
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}
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}
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pm_info->ddr_type = imx_mmdc_get_ddr_type();
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@ -610,3 +639,8 @@ void __init imx6sx_pm_init(void)
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{
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imx6_pm_common_init(&imx6sx_pm_data);
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}
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void __init imx6ul_pm_init(void)
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{
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imx6_pm_common_init(&imx6ul_pm_data);
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}
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@ -79,12 +79,15 @@
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/* sync L2 cache to drain L2's buffers to DRAM. */
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#ifdef CONFIG_CACHE_L2X0
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ldr r11, [r0, #PM_INFO_MX6Q_L2_V_OFFSET]
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teq r11, #0
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beq 6f
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mov r6, #0x0
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str r6, [r11, #L2X0_CACHE_SYNC]
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1:
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ldr r6, [r11, #L2X0_CACHE_SYNC]
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ands r6, r6, #0x1
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bne 1b
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6:
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#endif
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.endm
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47
include/linux/mfd/syscon/imx7-iomuxc-gpr.h
Normal file
47
include/linux/mfd/syscon/imx7-iomuxc-gpr.h
Normal file
@ -0,0 +1,47 @@
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/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __LINUX_IMX7_IOMUXC_GPR_H
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#define __LINUX_IMX7_IOMUXC_GPR_H
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#define IOMUXC_GPR0 0x00
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#define IOMUXC_GPR1 0x04
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#define IOMUXC_GPR2 0x08
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#define IOMUXC_GPR3 0x0c
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#define IOMUXC_GPR4 0x10
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#define IOMUXC_GPR5 0x14
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#define IOMUXC_GPR6 0x18
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#define IOMUXC_GPR7 0x1c
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#define IOMUXC_GPR8 0x20
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#define IOMUXC_GPR9 0x24
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#define IOMUXC_GPR10 0x28
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#define IOMUXC_GPR11 0x2c
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#define IOMUXC_GPR12 0x30
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#define IOMUXC_GPR13 0x34
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#define IOMUXC_GPR14 0x38
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#define IOMUXC_GPR15 0x3c
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#define IOMUXC_GPR16 0x40
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#define IOMUXC_GPR17 0x44
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#define IOMUXC_GPR18 0x48
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#define IOMUXC_GPR19 0x4c
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#define IOMUXC_GPR20 0x50
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#define IOMUXC_GPR21 0x54
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#define IOMUXC_GPR22 0x58
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/* For imx7d iomux gpr register field define */
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#define IMX7D_GPR1_IRQ_MASK (0x1 << 12)
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#define IMX7D_GPR1_ENET1_TX_CLK_SEL_MASK (0x1 << 13)
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#define IMX7D_GPR1_ENET2_TX_CLK_SEL_MASK (0x1 << 14)
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#define IMX7D_GPR1_ENET_TX_CLK_SEL_MASK (0x3 << 13)
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#define IMX7D_GPR1_ENET1_CLK_DIR_MASK (0x1 << 17)
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#define IMX7D_GPR1_ENET2_CLK_DIR_MASK (0x1 << 18)
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#define IMX7D_GPR1_ENET_CLK_DIR_MASK (0x3 << 17)
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#define IMX7D_GPR5_CSI_MUX_CONTROL_MIPI (0x1 << 4)
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#endif /* __LINUX_IMX7_IOMUXC_GPR_H */
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