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ARM: imx: Use INT_MEM_CLK_LPM as the bit name

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Bit 17 of register CCM_CGPR is called INT_MEM_CLK_LPM as per the mx6
reference manual, so use this name instead.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This commit is contained in:
Fabio Estevam 2014-01-07 08:00:40 -02:00 committed by Shawn Guo
parent c0bea59ca5
commit fa6be65ed4
3 changed files with 6 additions and 6 deletions
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2
arch/arm/mach-imx/common.h
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@ -139,7 +139,7 @@ void imx_anatop_init(void);
void imx_anatop_pre_suspend(void);
void imx_anatop_post_resume(void);
int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
void imx6q_set_chicken_bit(void);
void imx6q_set_int_mem_clk_lpm(void);
void imx_cpu_die(unsigned int cpu);
int imx_cpu_kill(unsigned int cpu);

4
arch/arm/mach-imx/cpuidle-imx6q.c
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@ -68,8 +68,8 @@ int __init imx6q_cpuidle_init(void)
/* Need to enable SCU standby for entering WAIT modes */
imx_scu_standby_enable();
/* Set chicken bit to get a reliable WAIT mode support */
imx6q_set_chicken_bit();
/* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */
imx6q_set_int_mem_clk_lpm();
return cpuidle_register(&imx6q_cpuidle_driver, NULL);
}

6
arch/arm/mach-imx/pm-imx6q.c
View File

@ -56,15 +56,15 @@
#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27)
#define CGPR 0x64
#define BM_CGPR_CHICKEN_BIT (0x1 << 17)
#define BM_CGPR_INT_MEM_CLK_LPM (0x1 << 17)
static void __iomem *ccm_base;
void imx6q_set_chicken_bit(void)
void imx6q_set_int_mem_clk_lpm(void)
{
u32 val = readl_relaxed(ccm_base + CGPR);
val |= BM_CGPR_CHICKEN_BIT;
val |= BM_CGPR_INT_MEM_CLK_LPM;
writel_relaxed(val, ccm_base + CGPR);
}