FEX-Emu/linux
1
0
Fork 0
mirror of https://github.com/FEX-Emu/linux.git synced 2025-02-14 08:19:28 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

drm/nouveau/core: allow representing method ranges in nouveau_omthds

Browse Source 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2012-11-07 16:28:35 +10:00
parent cbe7270d48
commit fb445b3c23
8 changed files with 116 additions and 115 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

184
drivers/gpu/drm/nouveau/core/engine/graph/nv04.c
View File

@ -787,168 +787,168 @@ nv01_graph_mthd_bind_chroma(struct nouveau_object *object, u32 mthd,
static struct nouveau_omthds
nv03_graph_gdi_omthds[] = {
{ 0x0184, nv01_graph_mthd_bind_patt },
{ 0x0188, nv04_graph_mthd_bind_rop },
{ 0x018c, nv04_graph_mthd_bind_beta1 },
{ 0x0190, nv04_graph_mthd_bind_surf_dst },
{ 0x02fc, nv04_graph_mthd_set_operation },
{ 0x0184, 0x0184, nv01_graph_mthd_bind_patt },
{ 0x0188, 0x0188, nv04_graph_mthd_bind_rop },
{ 0x018c, 0x018c, nv04_graph_mthd_bind_beta1 },
{ 0x0190, 0x0190, nv04_graph_mthd_bind_surf_dst },
{ 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
{}
};
static struct nouveau_omthds
nv04_graph_gdi_omthds[] = {
{ 0x0188, nv04_graph_mthd_bind_patt },
{ 0x018c, nv04_graph_mthd_bind_rop },
{ 0x0190, nv04_graph_mthd_bind_beta1 },
{ 0x0194, nv04_graph_mthd_bind_beta4 },
{ 0x0198, nv04_graph_mthd_bind_surf2d },
{ 0x02fc, nv04_graph_mthd_set_operation },
{ 0x0188, 0x0188, nv04_graph_mthd_bind_patt },
{ 0x018c, 0x018c, nv04_graph_mthd_bind_rop },
{ 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 },
{ 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 },
{ 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d },
{ 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
{}
};
static struct nouveau_omthds
nv01_graph_blit_omthds[] = {
{ 0x0184, nv01_graph_mthd_bind_chroma },
{ 0x0188, nv01_graph_mthd_bind_clip },
{ 0x018c, nv01_graph_mthd_bind_patt },
{ 0x0190, nv04_graph_mthd_bind_rop },
{ 0x0194, nv04_graph_mthd_bind_beta1 },
{ 0x0198, nv04_graph_mthd_bind_surf_dst },
{ 0x019c, nv04_graph_mthd_bind_surf_src },
{ 0x02fc, nv04_graph_mthd_set_operation },
{ 0x0184, 0x0184, nv01_graph_mthd_bind_chroma },
{ 0x0188, 0x0188, nv01_graph_mthd_bind_clip },
{ 0x018c, 0x018c, nv01_graph_mthd_bind_patt },
{ 0x0190, 0x0190, nv04_graph_mthd_bind_rop },
{ 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 },
{ 0x0198, 0x0198, nv04_graph_mthd_bind_surf_dst },
{ 0x019c, 0x019c, nv04_graph_mthd_bind_surf_src },
{ 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
{}
};
static struct nouveau_omthds
nv04_graph_blit_omthds[] = {
{ 0x0184, nv01_graph_mthd_bind_chroma },
{ 0x0188, nv01_graph_mthd_bind_clip },
{ 0x018c, nv04_graph_mthd_bind_patt },
{ 0x0190, nv04_graph_mthd_bind_rop },
{ 0x0194, nv04_graph_mthd_bind_beta1 },
{ 0x0198, nv04_graph_mthd_bind_beta4 },
{ 0x019c, nv04_graph_mthd_bind_surf2d },
{ 0x02fc, nv04_graph_mthd_set_operation },
{ 0x0184, 0x0184, nv01_graph_mthd_bind_chroma },
{ 0x0188, 0x0188, nv01_graph_mthd_bind_clip },
{ 0x018c, 0x018c, nv04_graph_mthd_bind_patt },
{ 0x0190, 0x0190, nv04_graph_mthd_bind_rop },
{ 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 },
{ 0x0198, 0x0198, nv04_graph_mthd_bind_beta4 },
{ 0x019c, 0x019c, nv04_graph_mthd_bind_surf2d },
{ 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
{}
};
static struct nouveau_omthds
nv04_graph_iifc_omthds[] = {
{ 0x0188, nv01_graph_mthd_bind_chroma },
{ 0x018c, nv01_graph_mthd_bind_clip },
{ 0x0190, nv04_graph_mthd_bind_patt },
{ 0x0194, nv04_graph_mthd_bind_rop },
{ 0x0198, nv04_graph_mthd_bind_beta1 },
{ 0x019c, nv04_graph_mthd_bind_beta4 },
{ 0x01a0, nv04_graph_mthd_bind_surf2d_swzsurf },
{ 0x03e4, nv04_graph_mthd_set_operation },
{ 0x0188, 0x0188, nv01_graph_mthd_bind_chroma },
{ 0x018c, 0x018c, nv01_graph_mthd_bind_clip },
{ 0x0190, 0x0190, nv04_graph_mthd_bind_patt },
{ 0x0194, 0x0194, nv04_graph_mthd_bind_rop },
{ 0x0198, 0x0198, nv04_graph_mthd_bind_beta1 },
{ 0x019c, 0x019c, nv04_graph_mthd_bind_beta4 },
{ 0x01a0, 0x01a0, nv04_graph_mthd_bind_surf2d_swzsurf },
{ 0x03e4, 0x03e4, nv04_graph_mthd_set_operation },
{}
};
static struct nouveau_omthds
nv01_graph_ifc_omthds[] = {
{ 0x0184, nv01_graph_mthd_bind_chroma },
{ 0x0188, nv01_graph_mthd_bind_clip },
{ 0x018c, nv01_graph_mthd_bind_patt },
{ 0x0190, nv04_graph_mthd_bind_rop },
{ 0x0194, nv04_graph_mthd_bind_beta1 },
{ 0x0198, nv04_graph_mthd_bind_surf_dst },
{ 0x02fc, nv04_graph_mthd_set_operation },
{ 0x0184, 0x0184, nv01_graph_mthd_bind_chroma },
{ 0x0188, 0x0188, nv01_graph_mthd_bind_clip },
{ 0x018c, 0x018c, nv01_graph_mthd_bind_patt },
{ 0x0190, 0x0190, nv04_graph_mthd_bind_rop },
{ 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 },
{ 0x0198, 0x0198, nv04_graph_mthd_bind_surf_dst },
{ 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
{}
};
static struct nouveau_omthds
nv04_graph_ifc_omthds[] = {
{ 0x0184, nv01_graph_mthd_bind_chroma },
{ 0x0188, nv01_graph_mthd_bind_clip },
{ 0x018c, nv04_graph_mthd_bind_patt },
{ 0x0190, nv04_graph_mthd_bind_rop },
{ 0x0194, nv04_graph_mthd_bind_beta1 },
{ 0x0198, nv04_graph_mthd_bind_beta4 },
{ 0x019c, nv04_graph_mthd_bind_surf2d },
{ 0x02fc, nv04_graph_mthd_set_operation },
{ 0x0184, 0x0184, nv01_graph_mthd_bind_chroma },
{ 0x0188, 0x0188, nv01_graph_mthd_bind_clip },
{ 0x018c, 0x018c, nv04_graph_mthd_bind_patt },
{ 0x0190, 0x0190, nv04_graph_mthd_bind_rop },
{ 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 },
{ 0x0198, 0x0198, nv04_graph_mthd_bind_beta4 },
{ 0x019c, 0x019c, nv04_graph_mthd_bind_surf2d },
{ 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
{}
};
static struct nouveau_omthds
nv03_graph_sifc_omthds[] = {
{ 0x0184, nv01_graph_mthd_bind_chroma },
{ 0x0188, nv01_graph_mthd_bind_patt },
{ 0x018c, nv04_graph_mthd_bind_rop },
{ 0x0190, nv04_graph_mthd_bind_beta1 },
{ 0x0194, nv04_graph_mthd_bind_surf_dst },
{ 0x02fc, nv04_graph_mthd_set_operation },
{ 0x0184, 0x0184, nv01_graph_mthd_bind_chroma },
{ 0x0188, 0x0188, nv01_graph_mthd_bind_patt },
{ 0x018c, 0x018c, nv04_graph_mthd_bind_rop },
{ 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 },
{ 0x0194, 0x0194, nv04_graph_mthd_bind_surf_dst },
{ 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
{}
};
static struct nouveau_omthds
nv04_graph_sifc_omthds[] = {
{ 0x0184, nv01_graph_mthd_bind_chroma },
{ 0x0188, nv04_graph_mthd_bind_patt },
{ 0x018c, nv04_graph_mthd_bind_rop },
{ 0x0190, nv04_graph_mthd_bind_beta1 },
{ 0x0194, nv04_graph_mthd_bind_beta4 },
{ 0x0198, nv04_graph_mthd_bind_surf2d },
{ 0x02fc, nv04_graph_mthd_set_operation },
{ 0x0184, 0x0184, nv01_graph_mthd_bind_chroma },
{ 0x0188, 0x0188, nv04_graph_mthd_bind_patt },
{ 0x018c, 0x018c, nv04_graph_mthd_bind_rop },
{ 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 },
{ 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 },
{ 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d },
{ 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
{}
};
static struct nouveau_omthds
nv03_graph_sifm_omthds[] = {
{ 0x0188, nv01_graph_mthd_bind_patt },
{ 0x018c, nv04_graph_mthd_bind_rop },
{ 0x0190, nv04_graph_mthd_bind_beta1 },
{ 0x0194, nv04_graph_mthd_bind_surf_dst },
{ 0x0304, nv04_graph_mthd_set_operation },
{ 0x0188, 0x0188, nv01_graph_mthd_bind_patt },
{ 0x018c, 0x018c, nv04_graph_mthd_bind_rop },
{ 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 },
{ 0x0194, 0x0194, nv04_graph_mthd_bind_surf_dst },
{ 0x0304, 0x0304, nv04_graph_mthd_set_operation },
{}
};
static struct nouveau_omthds
nv04_graph_sifm_omthds[] = {
{ 0x0188, nv04_graph_mthd_bind_patt },
{ 0x018c, nv04_graph_mthd_bind_rop },
{ 0x0190, nv04_graph_mthd_bind_beta1 },
{ 0x0194, nv04_graph_mthd_bind_beta4 },
{ 0x0198, nv04_graph_mthd_bind_surf2d },
{ 0x0304, nv04_graph_mthd_set_operation },
{ 0x0188, 0x0188, nv04_graph_mthd_bind_patt },
{ 0x018c, 0x018c, nv04_graph_mthd_bind_rop },
{ 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 },
{ 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 },
{ 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d },
{ 0x0304, 0x0304, nv04_graph_mthd_set_operation },
{}
};
static struct nouveau_omthds
nv04_graph_surf3d_omthds[] = {
{ 0x02f8, nv04_graph_mthd_surf3d_clip_h },
{ 0x02fc, nv04_graph_mthd_surf3d_clip_v },
{ 0x02f8, 0x02f8, nv04_graph_mthd_surf3d_clip_h },
{ 0x02fc, 0x02fc, nv04_graph_mthd_surf3d_clip_v },
{}
};
static struct nouveau_omthds
nv03_graph_ttri_omthds[] = {
{ 0x0188, nv01_graph_mthd_bind_clip },
{ 0x018c, nv04_graph_mthd_bind_surf_color },
{ 0x0190, nv04_graph_mthd_bind_surf_zeta },
{ 0x0188, 0x0188, nv01_graph_mthd_bind_clip },
{ 0x018c, 0x018c, nv04_graph_mthd_bind_surf_color },
{ 0x0190, 0x0190, nv04_graph_mthd_bind_surf_zeta },
{}
};
static struct nouveau_omthds
nv01_graph_prim_omthds[] = {
{ 0x0184, nv01_graph_mthd_bind_clip },
{ 0x0188, nv01_graph_mthd_bind_patt },
{ 0x018c, nv04_graph_mthd_bind_rop },
{ 0x0190, nv04_graph_mthd_bind_beta1 },
{ 0x0194, nv04_graph_mthd_bind_surf_dst },
{ 0x02fc, nv04_graph_mthd_set_operation },
{ 0x0184, 0x0184, nv01_graph_mthd_bind_clip },
{ 0x0188, 0x0188, nv01_graph_mthd_bind_patt },
{ 0x018c, 0x018c, nv04_graph_mthd_bind_rop },
{ 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 },
{ 0x0194, 0x0194, nv04_graph_mthd_bind_surf_dst },
{ 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
{}
};
static struct nouveau_omthds
nv04_graph_prim_omthds[] = {
{ 0x0184, nv01_graph_mthd_bind_clip },
{ 0x0188, nv04_graph_mthd_bind_patt },
{ 0x018c, nv04_graph_mthd_bind_rop },
{ 0x0190, nv04_graph_mthd_bind_beta1 },
{ 0x0194, nv04_graph_mthd_bind_beta4 },
{ 0x0198, nv04_graph_mthd_bind_surf2d },
{ 0x02fc, nv04_graph_mthd_set_operation },
{ 0x0184, 0x0184, nv01_graph_mthd_bind_clip },
{ 0x0188, 0x0188, nv04_graph_mthd_bind_patt },
{ 0x018c, 0x018c, nv04_graph_mthd_bind_rop },
{ 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 },
{ 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 },
{ 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d },
{ 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
{}
};

10
drivers/gpu/drm/nouveau/core/engine/graph/nv10.c
View File

@ -570,11 +570,11 @@ nv17_graph_mthd_lma_enable(struct nouveau_object *object, u32 mthd,
static struct nouveau_omthds
nv17_celcius_omthds[] = {
{ 0x1638, nv17_graph_mthd_lma_window },
{ 0x163c, nv17_graph_mthd_lma_window },
{ 0x1640, nv17_graph_mthd_lma_window },
{ 0x1644, nv17_graph_mthd_lma_window },
{ 0x1658, nv17_graph_mthd_lma_enable },
{ 0x1638, 0x1638, nv17_graph_mthd_lma_window },
{ 0x163c, 0x163c, nv17_graph_mthd_lma_window },
{ 0x1640, 0x1640, nv17_graph_mthd_lma_window },
{ 0x1644, 0x1644, nv17_graph_mthd_lma_window },
{ 0x1658, 0x1658, nv17_graph_mthd_lma_enable },
{}
};

6
drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c
View File

@ -121,9 +121,9 @@ nv31_mpeg_ofuncs = {
static struct nouveau_omthds
nv31_mpeg_omthds[] = {
{ 0x0190, nv31_mpeg_mthd_dma },
{ 0x01a0, nv31_mpeg_mthd_dma },
{ 0x01b0, nv31_mpeg_mthd_dma },
{ 0x0190, 0x0190, nv31_mpeg_mthd_dma },
{ 0x01a0, 0x01a0, nv31_mpeg_mthd_dma },
{ 0x01b0, 0x01b0, nv31_mpeg_mthd_dma },
{}
};

4
drivers/gpu/drm/nouveau/core/engine/software/nv04.c
View File

@ -63,8 +63,8 @@ nv04_software_flip(struct nouveau_object *object, u32 mthd,
static struct nouveau_omthds
nv04_software_omthds[] = {
{ 0x0150, nv04_software_set_ref },
{ 0x0500, nv04_software_flip },
{ 0x0150, 0x0150, nv04_software_set_ref },
{ 0x0500, 0x0500, nv04_software_flip },
{}
};

2
drivers/gpu/drm/nouveau/core/engine/software/nv10.c
View File

@ -52,7 +52,7 @@ nv10_software_flip(struct nouveau_object *object, u32 mthd,
static struct nouveau_omthds
nv10_software_omthds[] = {
{ 0x0500, nv10_software_flip },
{ 0x0500, 0x0500, nv10_software_flip },
{}
};

10
drivers/gpu/drm/nouveau/core/engine/software/nv50.c
View File

@ -117,11 +117,11 @@ nv50_software_mthd_flip(struct nouveau_object *object, u32 mthd,
static struct nouveau_omthds
nv50_software_omthds[] = {
{ 0x018c, nv50_software_mthd_dma_vblsem },
{ 0x0400, nv50_software_mthd_vblsem_offset },
{ 0x0404, nv50_software_mthd_vblsem_value },
{ 0x0408, nv50_software_mthd_vblsem_release },
{ 0x0500, nv50_software_mthd_flip },
{ 0x018c, 0x018c, nv50_software_mthd_dma_vblsem },
{ 0x0400, 0x0400, nv50_software_mthd_vblsem_offset },
{ 0x0404, 0x0404, nv50_software_mthd_vblsem_value },
{ 0x0408, 0x0408, nv50_software_mthd_vblsem_release },
{ 0x0500, 0x0500, nv50_software_mthd_flip },
{}
};

10
drivers/gpu/drm/nouveau/core/engine/software/nvc0.c
View File

@ -99,11 +99,11 @@ nvc0_software_mthd_flip(struct nouveau_object *object, u32 mthd,
static struct nouveau_omthds
nvc0_software_omthds[] = {
{ 0x0400, nvc0_software_mthd_vblsem_offset },
{ 0x0404, nvc0_software_mthd_vblsem_offset },
{ 0x0408, nvc0_software_mthd_vblsem_value },
{ 0x040c, nvc0_software_mthd_vblsem_release },
{ 0x0500, nvc0_software_mthd_flip },
{ 0x0400, 0x0400, nvc0_software_mthd_vblsem_offset },
{ 0x0404, 0x0404, nvc0_software_mthd_vblsem_offset },
{ 0x0408, 0x0408, nvc0_software_mthd_vblsem_value },
{ 0x040c, 0x040c, nvc0_software_mthd_vblsem_release },
{ 0x0500, 0x0500, nvc0_software_mthd_flip },
{}
};

5
drivers/gpu/drm/nouveau/core/include/core/object.h
View File

@ -70,7 +70,8 @@ nv_pclass(struct nouveau_object *parent, u32 oclass)
}
struct nouveau_omthds {
u32 method;
u32 start;
u32 limit;
int (*call)(struct nouveau_object *, u32, void *, u32);
};
@ -114,7 +115,7 @@ nv_exec(void *obj, u32 mthd, void *data, u32 size)
struct nouveau_omthds *method = nv_oclass(obj)->omthds;
while (method && method->call) {
if (method->method == mthd)
if (mthd >= method->start && mthd <= method->limit)
return method->call(obj, mthd, data, size);
method++;
}