mirror of
https://github.com/FEX-Emu/linux.git
synced 2024-12-21 00:42:16 +00:00
drm/i915: Avoid saving/restore the modesetting registers twice in KMS mode
In KMS mode we now use the normal mode-setting paths to set the modes back to the current configuration, so we don't need to also run the more limited non-KMS implementation of modesetting for resume. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Zhao Yakui
Eric Anholt
parent
af4fcb574e
commit
fccdaba431
@ -222,23 +222,12 @@ static void i915_restore_vga(struct drm_device *dev)
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I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK);
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}
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int i915_save_state(struct drm_device *dev)
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static void i915_save_modeset_reg(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int i;
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pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
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/* Render Standby */
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if (IS_I965G(dev) && IS_MOBILE(dev))
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dev_priv->saveRENDERSTANDBY = I915_READ(MCHBAR_RENDER_STANDBY);
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/* Hardware status page */
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dev_priv->saveHWS = I915_READ(HWS_PGA);
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/* Display arbitration control */
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dev_priv->saveDSPARB = I915_READ(DSPARB);
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if (drm_core_check_feature(dev, DRIVER_MODESET))
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return;
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/* Pipe & plane A info */
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dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
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dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
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@ -294,7 +283,122 @@ int i915_save_state(struct drm_device *dev)
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}
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i915_save_palette(dev, PIPE_B);
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dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT);
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return;
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}
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static void i915_restore_modeset_reg(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (drm_core_check_feature(dev, DRIVER_MODESET))
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return;
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/* Pipe & plane A info */
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/* Prime the clock */
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if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
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I915_WRITE(DPLL_A, dev_priv->saveDPLL_A &
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~DPLL_VCO_ENABLE);
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DRM_UDELAY(150);
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}
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I915_WRITE(FPA0, dev_priv->saveFPA0);
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I915_WRITE(FPA1, dev_priv->saveFPA1);
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/* Actually enable it */
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I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
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DRM_UDELAY(150);
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if (IS_I965G(dev))
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I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
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DRM_UDELAY(150);
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/* Restore mode */
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I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
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I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
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I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
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I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
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I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
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I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
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I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
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/* Restore plane info */
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I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
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I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
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I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
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I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR);
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I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
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if (IS_I965G(dev)) {
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I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
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I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
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}
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I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
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i915_restore_palette(dev, PIPE_A);
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/* Enable the plane */
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I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
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I915_WRITE(DSPAADDR, I915_READ(DSPAADDR));
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/* Pipe & plane B info */
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if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
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I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &
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~DPLL_VCO_ENABLE);
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DRM_UDELAY(150);
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}
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I915_WRITE(FPB0, dev_priv->saveFPB0);
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I915_WRITE(FPB1, dev_priv->saveFPB1);
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/* Actually enable it */
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I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
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DRM_UDELAY(150);
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if (IS_I965G(dev))
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I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
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DRM_UDELAY(150);
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/* Restore mode */
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I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
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I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
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I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
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I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
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I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
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I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
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I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
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/* Restore plane info */
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I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
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I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
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I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
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I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR);
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I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
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if (IS_I965G(dev)) {
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I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
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I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
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}
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I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
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i915_restore_palette(dev, PIPE_B);
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/* Enable the plane */
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I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
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I915_WRITE(DSPBADDR, I915_READ(DSPBADDR));
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return;
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}
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int i915_save_state(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int i;
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pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
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/* Render Standby */
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if (IS_I965G(dev) && IS_MOBILE(dev))
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dev_priv->saveRENDERSTANDBY = I915_READ(MCHBAR_RENDER_STANDBY);
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/* Hardware status page */
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dev_priv->saveHWS = I915_READ(HWS_PGA);
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/* Display arbitration control */
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dev_priv->saveDSPARB = I915_READ(DSPARB);
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/* This is only meaningful in non-KMS mode */
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/* Don't save them in KMS mode */
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i915_save_modeset_reg(dev);
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/* Cursor state */
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dev_priv->saveCURACNTR = I915_READ(CURACNTR);
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dev_priv->saveCURAPOS = I915_READ(CURAPOS);
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@ -430,92 +534,9 @@ int i915_restore_state(struct drm_device *dev)
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I915_WRITE(PIPEA_DP_LINK_N, dev_priv->savePIPEA_DP_LINK_N);
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I915_WRITE(PIPEB_DP_LINK_N, dev_priv->savePIPEB_DP_LINK_N);
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}
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/* Pipe & plane A info */
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/* Prime the clock */
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if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
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I915_WRITE(DPLL_A, dev_priv->saveDPLL_A &
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~DPLL_VCO_ENABLE);
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DRM_UDELAY(150);
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}
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I915_WRITE(FPA0, dev_priv->saveFPA0);
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I915_WRITE(FPA1, dev_priv->saveFPA1);
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/* Actually enable it */
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I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
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DRM_UDELAY(150);
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if (IS_I965G(dev))
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I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
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DRM_UDELAY(150);
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/* Restore mode */
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I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
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I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
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I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
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I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
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I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
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I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
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I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
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/* Restore plane info */
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I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
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I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
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I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
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I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR);
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I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
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if (IS_I965G(dev)) {
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I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
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I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
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}
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I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
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i915_restore_palette(dev, PIPE_A);
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/* Enable the plane */
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I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
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I915_WRITE(DSPAADDR, I915_READ(DSPAADDR));
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/* Pipe & plane B info */
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if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
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I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &
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~DPLL_VCO_ENABLE);
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DRM_UDELAY(150);
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}
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I915_WRITE(FPB0, dev_priv->saveFPB0);
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I915_WRITE(FPB1, dev_priv->saveFPB1);
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/* Actually enable it */
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I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
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DRM_UDELAY(150);
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if (IS_I965G(dev))
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I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
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DRM_UDELAY(150);
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/* Restore mode */
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I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
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I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
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I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
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I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
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I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
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I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
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I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
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/* Restore plane info */
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I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
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I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
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I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
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I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR);
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I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
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if (IS_I965G(dev)) {
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I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
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I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
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}
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I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
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i915_restore_palette(dev, PIPE_B);
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/* Enable the plane */
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I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
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I915_WRITE(DSPBADDR, I915_READ(DSPBADDR));
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/* This is only meaningful in non-KMS mode */
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/* Don't restore them in KMS mode */
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i915_restore_modeset_reg(dev);
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/* Cursor state */
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I915_WRITE(CURAPOS, dev_priv->saveCURAPOS);
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I915_WRITE(CURACNTR, dev_priv->saveCURACNTR);
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