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dt-bindings: Add the clock id of UART2 and MMC2 for Exynos3250

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This patch adds the new clock id for both UART2 and MM2 device
for Exynos3250 SoC.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This commit is contained in:
Chanwoo Choi 2016-03-31 11:47:58 +09:00 committed by Sylwester Nawrocki
parent f55532a0c0
commit fd00bbcddb
1 changed files with 10 additions and 1 deletions
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11
include/dt-bindings/clock/exynos3250.h
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@ -79,6 +79,8 @@
#define CLK_MOUT_CORE 58 #define CLK_MOUT_CORE 58
#define CLK_MOUT_APLL 59 #define CLK_MOUT_APLL 59
#define CLK_MOUT_ACLK_266_SUB 60 #define CLK_MOUT_ACLK_266_SUB 60
#define CLK_MOUT_UART2 61
#define CLK_MOUT_MMC2 62
/* Dividers */ /* Dividers */
#define CLK_DIV_GPL 64 #define CLK_DIV_GPL 64
@ -127,6 +129,9 @@
#define CLK_DIV_CORE 107 #define CLK_DIV_CORE 107
#define CLK_DIV_HPM 108 #define CLK_DIV_HPM 108
#define CLK_DIV_COPY 109 #define CLK_DIV_COPY 109
#define CLK_DIV_UART2 110
#define CLK_DIV_MMC2_PRE 111
#define CLK_DIV_MMC2 112
/* Gates */ /* Gates */
#define CLK_ASYNC_G3D 128 #define CLK_ASYNC_G3D 128
@ -223,6 +228,8 @@
#define CLK_BLOCK_MFC 219 #define CLK_BLOCK_MFC 219
#define CLK_BLOCK_CAM 220 #define CLK_BLOCK_CAM 220
#define CLK_SMIES 221 #define CLK_SMIES 221
#define CLK_UART2 222
#define CLK_SDMMC2 223
/* Special clocks */ /* Special clocks */
#define CLK_SCLK_JPEG 224 #define CLK_SCLK_JPEG 224
@ -249,12 +256,14 @@
#define CLK_SCLK_SPI0 245 #define CLK_SCLK_SPI0 245
#define CLK_SCLK_UART1 246 #define CLK_SCLK_UART1 246
#define CLK_SCLK_UART0 247 #define CLK_SCLK_UART0 247
#define CLK_SCLK_UART2 248
#define CLK_SCLK_MMC2 249
/* /*
* Total number of clocks of main CMU. * Total number of clocks of main CMU.
* NOTE: Must be equal to last clock ID increased by one. * NOTE: Must be equal to last clock ID increased by one.
*/ */
#define CLK_NR_CLKS 248 #define CLK_NR_CLKS 250
/* /*
* CMU DMC * CMU DMC