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drm/i915: Add eDP intermediate frequencies for CHV

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"P1273_DPLL_Programming Spreadsheet.xlsm" lists a boatload of
frequencies for eDP. Try to use them all.

For now I've decided not to add hardcoded DPLL dividers for these cases
since chv_find_best_dpll() works just fine.

I've not actually tested any of these since I don't have an eDP 1.4 panel.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Sonika Jindal <sonika.jindal@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä 2015-03-12 17:10:38 +02:00 committed by Daniel Vetter
parent e6bda3e4cb
commit fe51bfb95c
1 changed files with 6 additions and 0 deletions
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6
drivers/gpu/drm/i915/intel_dp.c
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@ -87,6 +87,9 @@ static const struct dp_link_dpll chv_dpll[] = {
/* Skylake supports following rates */
static const int gen9_rates[] = { 162000, 216000, 270000,
324000, 432000, 540000 };
static const int chv_rates[] = { 162000, 202500, 210000, 216000,
243000, 270000, 324000, 405000,
420000, 432000, 540000 };
static const int default_rates[] = { 162000, 270000, 540000 };
/**
@ -1148,6 +1151,9 @@ intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
if (INTEL_INFO(dev)->gen >= 9) {
*source_rates = gen9_rates;
return ARRAY_SIZE(gen9_rates);
} else if (IS_CHERRYVIEW(dev)) {
*source_rates = chv_rates;
return ARRAY_SIZE(chv_rates);
}
*source_rates = default_rates;