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x86, kexec: fix kexec x86 coding style
Impact: Cleanup Fix some coding style issue for kexec x86. Signed-off-by: Huang Ying <ying.huang@intel.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
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fef3a7a174
@ -14,12 +14,12 @@
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#include <linux/ftrace.h>
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#include <linux/suspend.h>
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#include <linux/gfp.h>
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#include <linux/io.h>
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#include <asm/pgtable.h>
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#include <asm/pgalloc.h>
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#include <asm/tlbflush.h>
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#include <asm/mmu_context.h>
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#include <asm/io.h>
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#include <asm/apic.h>
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#include <asm/cpufeature.h>
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#include <asm/desc.h>
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@ -63,7 +63,7 @@ static void load_segments(void)
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"\tmovl %%eax,%%fs\n"
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"\tmovl %%eax,%%gs\n"
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"\tmovl %%eax,%%ss\n"
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::: "eax", "memory");
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: : : "eax", "memory");
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#undef STR
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#undef __STR
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}
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@ -205,7 +205,8 @@ void machine_kexec(struct kimage *image)
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if (image->preserve_context) {
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#ifdef CONFIG_X86_IO_APIC
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/* We need to put APICs in legacy mode so that we can
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/*
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* We need to put APICs in legacy mode so that we can
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* get timer interrupts in second kernel. kexec/kdump
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* paths already have calls to disable_IO_APIC() in
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* one form or other. kexec jump path also need
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@ -227,7 +228,8 @@ void machine_kexec(struct kimage *image)
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page_list[PA_SWAP_PAGE] = (page_to_pfn(image->swap_page)
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<< PAGE_SHIFT);
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/* The segment registers are funny things, they have both a
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/*
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* The segment registers are funny things, they have both a
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* visible and an invisible part. Whenever the visible part is
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* set to a specific selector, the invisible part is loaded
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* with from a table in memory. At no other time is the
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@ -237,11 +239,12 @@ void machine_kexec(struct kimage *image)
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* segments, before I zap the gdt with an invalid value.
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*/
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load_segments();
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/* The gdt & idt are now invalid.
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/*
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* The gdt & idt are now invalid.
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* If you want to load them you must set up your own idt & gdt.
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*/
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set_gdt(phys_to_virt(0),0);
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set_idt(phys_to_virt(0),0);
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set_gdt(phys_to_virt(0), 0);
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set_idt(phys_to_virt(0), 0);
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/* now call it */
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image->start = relocate_kernel_ptr((unsigned long)image->head,
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@ -12,11 +12,11 @@
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#include <linux/reboot.h>
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#include <linux/numa.h>
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#include <linux/ftrace.h>
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#include <linux/io.h>
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#include <asm/pgtable.h>
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#include <asm/tlbflush.h>
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#include <asm/mmu_context.h>
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#include <asm/io.h>
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static void init_level2_page(pmd_t *level2p, unsigned long addr)
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{
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@ -83,9 +83,8 @@ static int init_level4_page(struct kimage *image, pgd_t *level4p,
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}
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level3p = (pud_t *)page_address(page);
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result = init_level3_page(image, level3p, addr, last_addr);
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if (result) {
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if (result)
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goto out;
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}
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set_pgd(level4p++, __pgd(__pa(level3p) | _KERNPG_TABLE));
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addr += PGDIR_SIZE;
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}
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@ -242,7 +241,8 @@ void machine_kexec(struct kimage *image)
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page_list[PA_TABLE_PAGE] =
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(unsigned long)__pa(page_address(image->control_code_page));
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/* The segment registers are funny things, they have both a
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/*
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* The segment registers are funny things, they have both a
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* visible and an invisible part. Whenever the visible part is
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* set to a specific selector, the invisible part is loaded
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* with from a table in memory. At no other time is the
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@ -252,11 +252,12 @@ void machine_kexec(struct kimage *image)
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* segments, before I zap the gdt with an invalid value.
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*/
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load_segments();
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/* The gdt & idt are now invalid.
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/*
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* The gdt & idt are now invalid.
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* If you want to load them you must set up your own idt & gdt.
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*/
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set_gdt(phys_to_virt(0),0);
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set_idt(phys_to_virt(0),0);
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set_gdt(phys_to_virt(0), 0);
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set_idt(phys_to_virt(0), 0);
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/* now call it */
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relocate_kernel((unsigned long)image->head, (unsigned long)page_list,
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@ -17,7 +17,8 @@
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#define PTR(x) (x << 2)
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/* control_page + KEXEC_CONTROL_CODE_MAX_SIZE
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/*
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* control_page + KEXEC_CONTROL_CODE_MAX_SIZE
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* ~ control_page + PAGE_SIZE are used as data storage and stack for
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* jumping back
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*/
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@ -76,8 +77,10 @@ relocate_kernel:
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movl %eax, CP_PA_SWAP_PAGE(%edi)
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movl %ebx, CP_PA_BACKUP_PAGES_MAP(%edi)
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/* get physical address of control page now */
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/* this is impossible after page table switch */
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/*
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* get physical address of control page now
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* this is impossible after page table switch
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*/
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movl PTR(PA_CONTROL_PAGE)(%ebp), %edi
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/* switch to new set of page tables */
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@ -97,7 +100,8 @@ identity_mapped:
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/* store the start address on the stack */
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pushl %edx
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/* Set cr0 to a known state:
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/*
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* Set cr0 to a known state:
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* - Paging disabled
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* - Alignment check disabled
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* - Write protect disabled
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@ -113,7 +117,8 @@ identity_mapped:
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/* clear cr4 if applicable */
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testl %ecx, %ecx
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jz 1f
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/* Set cr4 to a known state:
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/*
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* Set cr4 to a known state:
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* Setting everything to zero seems safe.
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*/
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xorl %eax, %eax
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@ -132,15 +137,18 @@ identity_mapped:
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call swap_pages
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addl $8, %esp
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/* To be certain of avoiding problems with self-modifying code
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/*
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* To be certain of avoiding problems with self-modifying code
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* I need to execute a serializing instruction here.
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* So I flush the TLB, it's handy, and not processor dependent.
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*/
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xorl %eax, %eax
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movl %eax, %cr3
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/* set all of the registers to known values */
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/* leave %esp alone */
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/*
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* set all of the registers to known values
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* leave %esp alone
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*/
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testl %esi, %esi
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jnz 1f
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@ -24,7 +24,8 @@
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.code64
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.globl relocate_kernel
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relocate_kernel:
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/* %rdi indirection_page
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/*
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* %rdi indirection_page
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* %rsi page_list
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* %rdx start address
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*/
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@ -33,8 +34,10 @@ relocate_kernel:
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pushq $0
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popfq
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/* get physical address of control page now */
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/* this is impossible after page table switch */
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/*
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* get physical address of control page now
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* this is impossible after page table switch
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*/
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movq PTR(PA_CONTROL_PAGE)(%rsi), %r8
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/* get physical address of page table now too */
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@ -55,7 +58,8 @@ identity_mapped:
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/* store the start address on the stack */
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pushq %rdx
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/* Set cr0 to a known state:
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/*
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* Set cr0 to a known state:
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* - Paging enabled
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* - Alignment check disabled
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* - Write protect disabled
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@ -68,7 +72,8 @@ identity_mapped:
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orl $(X86_CR0_PG | X86_CR0_PE), %eax
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movq %rax, %cr0
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/* Set cr4 to a known state:
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/*
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* Set cr4 to a known state:
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* - physical address extension enabled
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*/
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movq $X86_CR4_PAE, %rax
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@ -117,7 +122,8 @@ identity_mapped:
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jmp 0b
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3:
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/* To be certain of avoiding problems with self-modifying code
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/*
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* To be certain of avoiding problems with self-modifying code
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* I need to execute a serializing instruction here.
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* So I flush the TLB by reloading %cr3 here, it's handy,
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* and not processor dependent.
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@ -125,8 +131,10 @@ identity_mapped:
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movq %cr3, %rax
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movq %rax, %cr3
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/* set all of the registers to known values */
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/* leave %rsp alone */
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/*
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* set all of the registers to known values
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* leave %rsp alone
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*/
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xorq %rax, %rax
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xorq %rbx, %rbx
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