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ARM: Add Versatile Express CA9x4 processor support
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
parent
ceade897f3
commit
fef88f1076
@ -1,4 +1,9 @@
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menu "Versatile Express platform type"
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depends on ARCH_VEXPRESS
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config ARCH_VEXPRESS_CA9X4
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bool "Versatile Express Cortex-A9x4 tile"
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select CPU_V7
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select ARM_GIC
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endmenu
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@ -3,3 +3,4 @@
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#
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obj-y := v2m.o
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obj-$(CONFIG_ARCH_VEXPRESS_CA9X4) += ct-ca9x4.o
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215
arch/arm/mach-vexpress/ct-ca9x4.c
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215
arch/arm/mach-vexpress/ct-ca9x4.c
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@ -0,0 +1,215 @@
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/*
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* Versatile Express Core Tile Cortex A9x4 Support
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*/
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/clcd.h>
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#include <asm/clkdev.h>
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#include <asm/hardware/arm_timer.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/hardware/gic.h>
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#include <asm/mach-types.h>
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#include <mach/clkdev.h>
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#include <mach/ct-ca9x4.h>
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#include <plat/timer-sp.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include "core.h"
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#include <mach/motherboard.h>
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#define V2M_PA_CS7 0x10000000
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static struct map_desc ct_ca9x4_io_desc[] __initdata = {
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{
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.virtual = __MMIO_P2V(CT_CA9X4_MPIC),
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.pfn = __phys_to_pfn(CT_CA9X4_MPIC),
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.length = SZ_16K,
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.type = MT_DEVICE,
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}, {
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.virtual = __MMIO_P2V(CT_CA9X4_SP804_TIMER),
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.pfn = __phys_to_pfn(CT_CA9X4_SP804_TIMER),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = __MMIO_P2V(CT_CA9X4_L2CC),
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.pfn = __phys_to_pfn(CT_CA9X4_L2CC),
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.length = SZ_4K,
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.type = MT_DEVICE,
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},
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};
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static void __init ct_ca9x4_map_io(void)
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{
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v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
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}
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void __iomem *gic_cpu_base_addr;
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static void __init ct_ca9x4_init_irq(void)
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{
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gic_cpu_base_addr = MMIO_P2V(A9_MPCORE_GIC_CPU);
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gic_dist_init(0, MMIO_P2V(A9_MPCORE_GIC_DIST), 29);
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gic_cpu_init(0, gic_cpu_base_addr);
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}
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#if 0
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static void ct_ca9x4_timer_init(void)
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{
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writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
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writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
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sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1));
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sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0);
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}
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static struct sys_timer ct_ca9x4_timer = {
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.init = ct_ca9x4_timer_init,
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};
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#endif
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static struct clcd_panel xvga_panel = {
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.mode = {
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.name = "XVGA",
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.refresh = 60,
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.xres = 1024,
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.yres = 768,
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.pixclock = 15384,
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.left_margin = 168,
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.right_margin = 8,
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.upper_margin = 29,
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.lower_margin = 3,
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.hsync_len = 144,
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.vsync_len = 6,
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.sync = 0,
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.vmode = FB_VMODE_NONINTERLACED,
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},
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.width = -1,
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.height = -1,
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.tim2 = TIM2_BCD | TIM2_IPC,
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.cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
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.bpp = 16,
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};
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static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
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{
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v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);
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v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE_DB1, 2);
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}
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static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
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{
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unsigned long framesize = 1024 * 768 * 2;
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dma_addr_t dma;
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fb->panel = &xvga_panel;
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fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
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&dma, GFP_KERNEL);
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if (!fb->fb.screen_base) {
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printk(KERN_ERR "CLCD: unable to map frame buffer\n");
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return -ENOMEM;
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}
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fb->fb.fix.smem_start = dma;
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fb->fb.fix.smem_len = framesize;
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return 0;
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}
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static int ct_ca9x4_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
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{
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return dma_mmap_writecombine(&fb->dev->dev, vma, fb->fb.screen_base,
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fb->fb.fix.smem_start, fb->fb.fix.smem_len);
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}
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static void ct_ca9x4_clcd_remove(struct clcd_fb *fb)
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{
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dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
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fb->fb.screen_base, fb->fb.fix.smem_start);
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}
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static struct clcd_board ct_ca9x4_clcd_data = {
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.name = "CT-CA9X4",
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.check = clcdfb_check,
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.decode = clcdfb_decode,
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.enable = ct_ca9x4_clcd_enable,
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.setup = ct_ca9x4_clcd_setup,
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.mmap = ct_ca9x4_clcd_mmap,
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.remove = ct_ca9x4_clcd_remove,
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};
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static AMBA_DEVICE(clcd, "ct:clcd", CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data);
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static AMBA_DEVICE(dmc, "ct:dmc", CT_CA9X4_DMC, NULL);
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static AMBA_DEVICE(smc, "ct:smc", CT_CA9X4_SMC, NULL);
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static AMBA_DEVICE(gpio, "ct:gpio", CT_CA9X4_GPIO, NULL);
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static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
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&clcd_device,
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&dmc_device,
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&smc_device,
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&gpio_device,
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};
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static long ct_round(struct clk *clk, unsigned long rate)
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{
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return rate;
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}
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static int ct_set(struct clk *clk, unsigned long rate)
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{
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return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_DB1 | 1, rate);
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}
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static const struct clk_ops osc1_clk_ops = {
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.round = ct_round,
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.set = ct_set,
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};
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static struct clk osc1_clk = {
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.ops = &osc1_clk_ops,
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.rate = 24000000,
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};
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static struct clk_lookup lookups[] = {
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{ /* CLCD */
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.dev_id = "ct:clcd",
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.clk = &osc1_clk,
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},
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};
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static void ct_ca9x4_init(void)
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{
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int i;
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#ifdef CONFIG_CACHE_L2X0
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l2x0_init(MMIO_P2V(CT_CA9X4_L2CC), 0x00000000, 0xfe0fffff);
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#endif
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
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amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
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}
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MACHINE_START(VEXPRESS, "ARM-Versatile Express CA9x4")
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.phys_io = V2M_UART0,
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.io_pg_offst = (__MMIO_P2V(V2M_UART0) >> 18) & 0xfffc,
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.boot_params = PHYS_OFFSET + 0x00000100,
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.map_io = ct_ca9x4_map_io,
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.init_irq = ct_ca9x4_init_irq,
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#if 0
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.timer = &ct_ca9x4_timer,
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#else
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.timer = &v2m_timer,
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#endif
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.init_machine = ct_ca9x4_init,
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MACHINE_END
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43
arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
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43
arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
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@ -0,0 +1,43 @@
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#ifndef __MACH_CT_CA9X4_H
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#define __MACH_CT_CA9X4_H
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/*
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* Physical base addresses
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*/
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#define CT_CA9X4_CLCDC (0x10020000)
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#define CT_CA9X4_AXIRAM (0x10060000)
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#define CT_CA9X4_DMC (0x100e0000)
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#define CT_CA9X4_SMC (0x100e1000)
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#define CT_CA9X4_SCC (0x100e2000)
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#define CT_CA9X4_SP804_TIMER (0x100e4000)
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#define CT_CA9X4_SP805_WDT (0x100e5000)
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#define CT_CA9X4_TZPC (0x100e6000)
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#define CT_CA9X4_GPIO (0x100e8000)
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#define CT_CA9X4_FASTAXI (0x100e9000)
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#define CT_CA9X4_SLOWAXI (0x100ea000)
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#define CT_CA9X4_TZASC (0x100ec000)
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#define CT_CA9X4_CORESIGHT (0x10200000)
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#define CT_CA9X4_MPIC (0x1e000000)
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#define CT_CA9X4_SYSTIMER (0x1e004000)
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#define CT_CA9X4_SYSWDT (0x1e007000)
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#define CT_CA9X4_L2CC (0x1e00a000)
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#define CT_CA9X4_TIMER0 (CT_CA9X4_SP804_TIMER + 0x000)
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#define CT_CA9X4_TIMER1 (CT_CA9X4_SP804_TIMER + 0x020)
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#define A9_MPCORE_SCU (CT_CA9X4_MPIC + 0x0000)
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#define A9_MPCORE_GIC_CPU (CT_CA9X4_MPIC + 0x0100)
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#define A9_MPCORE_GIT (CT_CA9X4_MPIC + 0x0200)
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#define A9_MPCORE_GIC_DIST (CT_CA9X4_MPIC + 0x1000)
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/*
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* Interrupts. Those in {} are for AMBA devices
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*/
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#define IRQ_CT_CA9X4_CLCDC { 76 }
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#define IRQ_CT_CA9X4_DMC { -1 }
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#define IRQ_CT_CA9X4_SMC { 77, 78 }
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#define IRQ_CT_CA9X4_TIMER0 80
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#define IRQ_CT_CA9X4_TIMER1 81
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#define IRQ_CT_CA9X4_GPIO { 82 }
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#endif
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@ -754,7 +754,8 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
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config CACHE_L2X0
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bool "Enable the L2x0 outer cache controller"
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depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
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REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK || ARCH_OMAP4
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REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \
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ARCH_NOMADIK || ARCH_OMAP4 || ARCH_VEXPRESS_CA9X4
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default y
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select OUTER_CACHE
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help
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