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MIPS: Move 'gic_present' to common location.
Move the global variable 'gic_present' to be defined in the file 'arch/mips/kernel/irq-gic.c' instead of defining it individually for each platform making use of the GIC. Also change the type to be an unsigned integer instead of signed. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
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451b001b05
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ff86714fda
arch/mips
@ -359,7 +359,7 @@ struct gic_shared_intr_map {
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/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
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#define GIC_PIN_TO_VEC_OFFSET (1)
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extern int gic_present;
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extern unsigned int gic_present;
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extern unsigned long _gic_base;
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extern unsigned int gic_irq_base;
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extern unsigned int gic_irq_flags[];
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@ -19,6 +19,7 @@
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#include <linux/hardirq.h>
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#include <asm-generic/bitops/find.h>
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unsigned int gic_present;
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unsigned long _gic_base;
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unsigned int gic_irq_base;
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unsigned int gic_irq_flags[GIC_NUM_INTRS];
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@ -34,6 +34,7 @@
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#include <asm/mipsregs.h>
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#include <asm/mipsmtregs.h>
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#include <asm/mips_mt.h>
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#include <asm/gic.h>
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static void __init smvp_copy_vpe_config(void)
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{
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@ -151,8 +152,6 @@ static void vsmp_send_ipi_mask(const struct cpumask *mask, unsigned int action)
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static void __cpuinit vsmp_init_secondary(void)
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{
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#ifdef CONFIG_IRQ_GIC
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extern int gic_present;
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/* This is Malta specific: IPI,performance and timer interrupts */
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if (gic_present)
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change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 |
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@ -47,7 +47,6 @@
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#include <asm/setup.h>
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int gcmp_present = -1;
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int gic_present;
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static unsigned long _msc01_biu_base;
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static unsigned long _gcmp_base;
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static unsigned int ipi_map[NR_CPUS];
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@ -20,7 +20,6 @@
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#define SEAD_CONFIG_BASE 0x1b100110
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#define SEAD_CONFIG_SIZE 4
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int gic_present;
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static unsigned long sead3_config_reg;
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/*
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