as a module
Without a GPL-compatible license this driver cannot be built as a module,
because the platform_driver_* API is only exported to GPL modules.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@pengutronix.de>
Acked-by: Eric Miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Currently PWM0/2 (pxa27x_device_pwm0 at 0x40b00000 and 0x40b00010
are registered as as pwm_id 0 and 1, PWM1/3 (pxa27x_device_pwm1 at
0x40c00000 and 0x40c00010) are registered as pwm_id 2 and 3.
This patch corrects the pwm_ids to match the documented register names.
Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com>
Acked-by: Eric Miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch adds support for DPLL autoidle control to the OMAP3 clock
framework. These functions will be used by the noncore DPLL enable
and disable code - this is because, according to the CDP code, the
DPLL autoidle status must be saved and restored across DPLL
lock/bypass/off transitions.
N.B.: the CORE DPLL (DPLL3) has three autoidle mode options, rather
than just two. This code currently does not support the third option,
low-power bypass autoidle.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add a new OMAP chip identification interface, omap_chip_id.
omap_chip_id is a structure which contains one bit for each OMAP2/3
CPU type, and on 3430, ES level. For example, the CHIP_IS_OMAP2420
bit is set in omap_chip at boot on an OMAP2420. On OMAP3430ES2, both
CHIP_IS_OMAP3430 and CHIP_IS_OMAP3430ES2 bits are set.
omap_chip is set in mach-omap2/id.c by _set_omap_chip(). Other
code should use the omap_chip_is() function to test against omap_chip.
Also, clean up id.c by splitting some code out of
omap_check_revision() into its own function, _set_system_rev(); and
converting some debug printk()s into pr_debug().
Second revision.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
New struct omap_globals contains the omap processor specific
module bases. Use omap_globals to set the various base addresses
to make detecting omap chip type simpler.
Also introduce OMAP1_IO_ADDRESS and OMAP2_IO_ADDRESS for future multi-omap
patches.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Change omap USB code to use omap_read/write instead of __REG for multi-omap
Cc: David Brownell <david-b@pacbell.net>
Cc: linux-usb@vger.kernel.org
Cc: i2c@lm-sensors.org
Signed-off-by: Tony Lindgren <tony@atomide.com>
Change omap_cf.c and omap_nor.c to use omap_readw/writew instead of __REG.
This is needed for multi-omap in the future.
Cc: David Brownell <david-b@pacbell.net>
Cc: linux-pcmcia@lists.infradead.org
Cc: linux-mtd@lists.infradead.org
Signed-off-by: Tony Lindren <tony@atomide.com>
debugfs can provide the infrastructure to trace the dependencies of
clock tree hierarchy quite visibly. This patch enables to keep track
of clock tree hierarchy and expose their attributes under each clock
directry as below:
omap:~# tree -d -L 2 /debug/clock/omap_32k_fck/
/debug/clock/omap_32k_fck/
|-- gpt10_fck
|-- gpt11_fck
|-- gpt1_fck
|-- per_32k_alwon_fck
| |-- gpio2_fck
| |-- gpio3_fck
| |-- gpio4_fck
| |-- gpio5_fck
| |-- gpio6_fck
| `-- wdt3_fck
|-- ts_fck
`-- wkup_32k_fck
|-- gpio1_fck
`-- wdt2_fck
14 directories
omap:~# tree /debug/clock/omap_32k_fck/gpt10_fck/
/debug/clock/omap_32k_fck/gpt10_fck/
|-- flags
|-- rate
`-- usecount
0 directories, 3 files
Although, compared with David Brownell's small patch, this may look
bit overkilling, I expect that this debugfs can deal with other PRCM
complexities at the same time. For example, powerdomain dependencies
can be expressed by using symbolic links of these clocks if
powerdomain supports dubgfs as well.
Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
If boards with different NR_IRQS are compiled together, tons of
compiler warnings are emitted about redefining NR_IRQS.
This patch fixes the problem by adding up NR_IRQS in a common place.
Patch also removes quite a bit of now unnecessary code.
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch adds support for mach-omap2 based on current
mcbsp platform driver.
Signed-off-by: Eduardo Valentin <eduardo.valentin@indt.org.br>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch adds support for mach-omap1 based on current
mcbsp platform driver.
Signed-off-by: Eduardo Valentin <eduardo.valentin@indt.org.br>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch transform mcbsp code to use platform data
from arch/arm/plat-omap/devices.c
It also gets ride of ifdefs on mcbsp.c code.
To do it, a platform data structure was defined.
Signed-off-by: Eduardo Valentin <eduardo.valentin@indt.org.br>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch fix lots of warnings and errors reported by
scripts/checkpatch.pl on arch/arm/plat-omap/mcbsp.c.
Signed-off-by: Eduardo Valentin <eduardo.valentin@indt.org.br>
Acked-by: Felipe Balbi <felipe.balbi@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Remove __REG access in DMA code, use dma_read/write instead:
- dynamically set the omap_dma_base based on the omap type
- omap_read/write becomes dma_read/write
- dma channel registers are read with dma_ch_read/write
Cc: David Brownell <david-b@pacbell.net>
Cc: linux-usb@vger.kernel.org
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch optimizes the timer load and start sequence. By combining the
load and start a needless posted wait can be removed from the system timer
execution path.
* Before patch register writes are taking up .078% @ 500MHz during idle.
Address |total |min |max |avr |count|ratio%
old\process\default_idle|7.369s |0.0us|999.902ms|14.477ms|509. |62.661%
ld\Global\cpu_v7_do_idle|4.265s |0.0us|375.786ms|24.374ms|175. |36.270%
(UNKNOWN)|17.503ms|0.us|531.080us|5.119us|3419. |0.148%
r\omap_dm_timer_set_load|8.135ms|0.0us|79.887us|15.065us|540. |0.069% <--
\vmlinux-old\Global\_end|2.023ms|0.0us|4.000us|0.560us|3613. |0.017%
-old\Global\__raw_readsw|1.962ms|0.0us|108.610us|9.167us|214. |0.016%
old\smc91x\smc_interrupt|1.353ms|0.0us|10.212us|2.348us|576. |0.011%
s/namei\__link_path_walk|1.161ms|0.0us|4.310us|0.762us| 1524. |0.009%
\omap_dm_timer_write_reg|1.085ms|0.0us|126.150us|2.153us|504. |0.009% <--
* After patch timer functions do not show up in top listings for long captures.
Signed-off-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch adds the use of write posting for the timer. Previously, every
write could lock the requestor for almost 3x32KHz cycles. This patch only
synchronizes before writes and reads instead of after them and it does
it on per register basis. Doing it this way there is some chance to hide
some of the sync latency. It also removes some needless reads when
non-posted mode is there. With out this fix the read/writes take almost
2% CPU load @500MHz just waiting on tick timer registers.
Also define new 34xx only registers.
Signed-off-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Andrew Morton reported this against linux-next:
ERROR: ".save_stack_trace" [tests/backtracetest.ko] undefined!
Reported-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
The Cardbus connector does not have an IDSEL signal, and Cardbus
cards are always the intended target of configuration transactions
on their local PCI bus. This means that if the Orion's PCI bus
signals are hooked up to a Cardbus slot, the same set of PCI
functions will will appear 31 times, for each of the PCI device
IDs 1-31 (ID 0 is the host bridge).
This patch adds a function to the Orion PCI handling code that board
support code can call to enable Cardbus mode. When Cardbus mode is
enabled, configuration transactions on the PCI local bus are only
allowed to PCI IDs 0 (host bridge) and 1 (cardbus device).
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
This patch allows booting Kirkwood with the L2 in writeback mode,
by reading the WT override bit from the L2 config register and
passing that into the Feroceon L2 init routine, instead of assuming
that the WT override bit will always be set
Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
In some cases, compilation of the tsx09 common file was failing due
to an incomplete list of includes.
Signed-off-by: Sylver Bruneau <sylver.bruneau@googlemail.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
After Jean Delvare's change "i2c: Convert most new-style drivers
to use module aliasing" (3760f736716f74bdc62a4ba5406934338da93eb2),
loading rtc-xxx from platform code fails. Update mv2120-setup.c so
that the driver is loaded correctly.
Signed-off-by: Martin Michlmayr <tbm@cyrius.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Kurobox Pro/Linkstation Pro devices use a microcontroller connected
to UART1. As most of the communication with this microcontroller is
done from userland (power button detection, fan speed ...), the setup
file has to make UART1 available from userland.
Signed-off-by: Sylver Bruneau <sylver.bruneau@googlemail.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
This patch annotates the platform_secondary_init function in
arch/arm/mach-realview/platsmp.c with trace_hardirqs_off to avoid a
warning when LOCKDEP and TRACE_IRQFLAGS are enabled.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
It's not even passed on to smp_call_function() anymore, since that
was removed. So kill it.
Acked-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
Reviewed-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Signed-off-by: Jens Axboe <jens.axboe@oracle.com>
It's never used and the comments refer to nonatomic and retry
interchangably. So get rid of it.
Acked-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
Signed-off-by: Jens Axboe <jens.axboe@oracle.com>
This converts arm to use the new helpers for smp_call_function() and
friends, and adds support for smp_call_function_single().
Fixups and testing done by Catalin Marinas <catalin.marinas@arm.com>
Cc: Russell King <rmk@arm.linux.org.uk>
Signed-off-by: Jens Axboe <jens.axboe@oracle.com>
Record the address of the mcount call-site. Currently all archs except sparc64
record the address of the instruction following the mcount call-site. Some
general cleanups are entailed. Storing mcount addresses in rec->ip enables
looking them up in the kprobe hash table later on to check if they're kprobe'd.
Signed-off-by: Abhishek Sagar <sagar.abhishek@gmail.com>
Cc: davem@davemloft.net
Cc: Steven Rostedt <rostedt@goodmis.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
The Discovery Duo (MV78xx0) has two x4 PCIe ports which can either
be used in x4 mode or in quad x1 mode. This patch adds an accessor
function to the generic plat-orion PCIe handling code to detect in
which of the two modes we're running (which is determined by strap
pins and/or configured by the bootloader).
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Add support for the Feroceon 88fr571-vd CPU core as found in e.g.
the Marvell Discovery Duo family of ARM SoCs.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
The Marvell Kirkwood (88F6000) is a family of ARM SoCs based on a
Shiva CPU core, and features a DDR2 controller, a x1 PCIe interface,
a USB 2.0 interface, a SPI controller, a crypto accelerator, a TS
interface, and IDMA/XOR engines, and depending on the model, also
features one or two Gigabit Ethernet interfaces, two SATA II
interfaces, one or two TWSI interfaces, one or two UARTs, a
TDM/SLIC interface, a NAND controller, an I2S/SPDIF interface, and
an SDIO interface.
This patch adds supports for the Marvell DB-88F6281-BP Development
Board and the RD-88F6192-NAS and the RD-88F6281 Reference Designs,
enabling support for the PCIe interface, the USB interface, the
ethernet interfaces, the SATA interfaces, the TWSI interfaces, the
UARTs, and the NAND controller.
Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Add support for the Shiva 88fr131 CPU core as found in e.g. the
Marvell Kirkwood family of ARM SoCs.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
This patch adds support for the unified Feroceon L2 cache controller
as found in e.g. the Marvell Kirkwood and Marvell Discovery Duo
families of ARM SoCs.
Note that:
- Page table walks are outer uncacheable on Kirkwood and Discovery
Duo, since the ARMv5 spec provides no way to indicate outer
cacheability of page table walks (specifying it in TTBR[4:3] is
an ARMv6+ feature).
This requires adding L2 cache clean instructions to
proc-feroceon.S (dcache_clean_area(), set_pte()) as well as to
tlbflush.h ({flush,clean}_pmd_entry()). The latter case is handled
by defining a new TLB type (TLB_FEROCEON) which is almost identical
to the v4wbi one but provides a TLB_L2CLEAN_FR flag.
- The Feroceon L2 cache controller supports L2 range (i.e. 'clean L2
range by MVA' and 'invalidate L2 range by MVA') operations, and this
patch uses those range operations for all Linux outer cache
operations, as they are faster than the regular per-line operations.
L2 range operations are not interruptible on this hardware, which
avoids potential livelock issues, but can be bad for interrupt
latency, so there is a compile-time tunable (MAX_RANGE_SIZE) which
allows you to select the maximum range size to operate on at once.
(Valid range is between one cache line and one 4KiB page, and must
be a multiple of the line size.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
This patch adds support for the L1 D cache range operations that
are supported by the Marvell Discovery Duo and Marvell Kirkwood
ARM SoCs.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Acked-by: Saeed Bishara <saeed@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
The Marvell Loki (88RC8480) is an ARM SoC based on a Feroceon CPU
core running at between 400 MHz and 1.0 GHz, and features a 64 bit
DDR controller, 512K of internal SRAM, two x4 PCI-Express ports,
two Gigabit Ethernet ports, two 4x SAS/SATA controllers, two UARTs,
two TWSI controllers, and IDMA/XOR engines.
This patch adds support for the Marvell LB88RC8480 Development
Board, enabling the use of the PCIe interfaces, the ethernet
interfaces, the TWSI interfaces and the UARTs.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Some Feroceon-based SoCs have an MBUS bridge interrupt controller
that requires writing a one instead of a zero to clear edge
interrupt sources such as timer expiry.
This patch adds a new BRIDGE_INT_TIMER1_CLR define, which platform
code can set to either ~BRIDGE_INT_TIMER1 (write-zero-to-clear) or
BRIDGE_INT_TIMER1 (write-one-to-clear) depending on the platform.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
There are a couple more Feroceon-based SoCs out in the field that use
different Variant and Architecture fields in their Main ID registers
-- this patch tweaks the processor match/mask in proc-feroceon.S to
catch those SoCs as well.
Signed-off-by: Ke Wei <kewei@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tweak the Feroceon match/mask in arch/arm/boot/compressed/head.S to
match a couple of newer Feroceon cores (such as the 88fr571vd with
CPU ID 0x56155710, and the 88fr131 with CPU ID 0x56251310) as well.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
