16z135 IP Core has changed so the driver needs to be updated to respect
these changes. The following changes have been made:
* Don't invert the 16z135 modem status register when reading.
* Add module parameter to configure the (baud rate dependent) RX timeout.
Character timeout in seconds = (timeout_reg * baud_reg * 4)/freq_reg.
* Enable the handling of UART core's automatic flow control feature.
When AFE is active disable generation of modem status IRQs.
* Rework the handling of IRQs to be conform with newer FPGA versions and
take precautions not to miss an interrupt because of the destructive read
of the IIR register.
* Correct men_z135_handle_modem_status(), MSR is stat_reg[15:8] not
stat_reg[7:0]
* Correct calling of uart_handle_{dcd,cts}_change()
* Reset CLOCAL when CRTSCTS is set
Signed-off-by: Johannes Thumshirn <johannes.thumshirn@men.de>
Reviewed-by: Peter Hurley <peter@hurleysoftware.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The mcb_device_id table is supposed to be zero-terminated.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Cc: stable <stable@vger.kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Call uart_write_wakeup() after writing the hardware FIFO and updateing the FIFO
pointers.
This fixes high latency and jitter on PPP over Serial links.
Reported-by: Jun Shih <Jun.Shih@pason.com>
Tested-by: Jun Shih <Jun.Shih@pason.com>
Signed-off-by: Johannes Thumshirn <johannes.thumshirn@men.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Don't activate the TX Space available IRQ on startup, or a simple
$ cat /dev/ttyHSU0
will cause an endless amount of IRQs, as there is always space in
the TX FIFO available if no data is going to be sent.
Also correct comments for IRQ names (RX and TX swapped).
Signed-off-by: Johannes Thumshirn <johannes.thumshirn@men.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Add driver for MEN's 16z135 High Speed UART.
The 16z135 is a memory mapped UART Core on an MCB FPGA and has 1024 byte
deep FIFO buffers for the RX and TX path. It also has configurable FIFO
fill level IRQs and data copied to and from the hardware has to be
acknowledged.
Signed-off-by: Johannes Thumshirn <johannes.thumshirn@men.de>
Reviewed-by: Alan Cox <gnomes@lxorguk.ukuu.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
