Commit Graph

2675 Commits

Author SHA1 Message Date
Yong Zhang
cad9bc6904 MIPS: 64-bit: Fix o32 core dump
If an o32 process generates a core dump on a 64 bit kernel, the core file
will not be correctly recognized. This is because ELF_CORE_COPY_REGS and
ELF_CORE_COPY_TASK_REGS are not correctly defined for o32 and will use
the default register set which would be CONFIG_64BIT in asm/elf.h.

So we'll switch to use the right register defines in this situation by
checking for WANT_COMPAT_REG_H and use the right defines of
ELF_CORE_COPY_REGS and ELF_CORE_COPY_TASK_REGS.

[Ralf: made ELF_CORE_COPY_TASK_REGS() bullet-proof against funny arguments.]

Signed-off-by: Yong Zhang <yong.zhang@windriver.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-07-03 15:45:27 +01:00
Tim Anderson
eb9b5141a9 MIPS: CMP: Update sync-r4k for current kernel
This revises the sync-4k so it will boot and operate since the removal of
expirelo from the timer code.

Signed-off-by: Tim Anderson <tanderson@mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-07-03 15:45:27 +01:00
Tim Anderson
47b178bb69 MIPS: CMP: Move gcmp_probe to before the SMP ops
This is to move the gcmp_probe call to before the use of and selection of
the smp_ops functions. This allows malta with 1004K to work.

Signed-off-by: Tim Anderson <tanderson@mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-07-03 15:45:26 +01:00
Tim Anderson
0365070f05 MIPS: CMP: activate CMP support
Most of the CMP support was added before, this mostly correct compile
problems but adds a platform specific translation for the interrupt number
based on cpu number.

Signed-off-by: Tim Anderson <tanderson@mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-07-03 15:45:26 +01:00
Tim Anderson
a214cef9a5 MIPS: CMP: Extend IPI handling to CPU number
This takes the current IPI interrupt assignment from the fix number of 4
to the number of CPUs defined in the system.

Signed-off-by: Tim Anderson <tanderson@mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-07-03 15:45:26 +01:00
Tim Anderson
9306c8def6 MIPS: CMP: Extend the GIC IPI interrupts beyond 32
This patch extends the GIC interrupt handling beyond the current 32 bit
range as well as extending the number of interrupts based on the number
of CPUs.

Signed-off-by: Tim Anderson <tanderson@mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-07-03 15:45:25 +01:00
David Daney
b53d4d1f8d MIPS: Define __arch_swab64 for all mips r2 cpus
Some CPUs implement mipsr2, but because they are a super-set of mips64r2 do
not define CONFIG_CPU_MIPS64_R2.  Cavium OCTEON falls into this category.
We would still like to use the optimized implementation, so since we have
already checked for CONFIG_CPU_MIPSR2, checking for CONFIG_64BIT instead of
CONFIG_CPU_MIPS64_R2 is sufficient.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-07-03 15:45:25 +01:00
Yoichi Yuasa
27fdd325da MIPS: Update VR41xx GPIO driver to use gpiolib
Signed-off-by: Yoichi Yuasa <yyuasa@linux.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-07-03 15:45:25 +01:00
David Daney
69f16c9a86 MIPS: Hookup new syscalls sys_rt_tgsigqueueinfo and sys_perf_counter_open.
[Ralf: I fixed up the numbering in the comment in scall64-n32.S.]

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-07-03 15:45:24 +01:00
Dmitri Vorobiev
d7e014db37 MIPS: Malta: Remove unnecessary function prototypes
Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@movial.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-07-03 15:45:24 +01:00
Joe Perches
52a7a27cd8 MIPS: MT: Remove unnecessary semicolons
Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-07-03 15:45:23 +01:00
Florian Fainelli
7ca5dc145b MIPS: Add support for Texas Instruments AR7 System-on-a-Chip
This patch adds support for the Texas Instruments AR7 System-on-a-Chip.
It supports the TNETD7100, 7200 and 7300 versions of the SoC.

Signed-off-by: Matteo Croce <matteo@openwrt.org>
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: Eugene Konev <ejka@openwrt.org>
Signed-off-by: Nicolas Thill <nico@openwrt.org>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-07-03 15:45:23 +01:00
Ralf Baechle
773cb77d0e MIPS: Cavium: Add CPU hotplugging code.
Thanks to Cavium Inc. for the code contribution and help.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-24 18:34:40 +01:00
Ralf Baechle
9801b321ec MIPS: SMP: Allow suspend and hibernation if CPU hotplug is available
The SMP implementation of suspend and hibernate depends on CPU hotplugging.
In the past we didn't have CPU hotplug so suspend and hibernation were not
possible on SMP systems.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-24 18:34:40 +01:00
Ralf Baechle
1b2bc75c1b MIPS: Add arch generic CPU hotplug
Each platform has to add support for CPU hotplugging itself by providing
suitable definitions for the cpu_disable and cpu_die of the smp_ops
methods and setting SYS_SUPPORTS_HOTPLUG_CPU.  A platform should only set
SYS_SUPPORTS_HOTPLUG_CPU once all it's smp_ops definitions have the
necessary changes.  This patch contains the changes to the dummy smp_ops
definition for uni-processor systems.

Parts of the code contributed by Cavium Inc.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-24 18:34:40 +01:00
Ralf Baechle
2e25406fb8 MIPS: Sibyte: Fix build error if CONFIG_SERIAL_SB1250_DUART is undefined.
This fixes kernel.org bugzilla 13596, see
http://bugzilla.kernel.org/show_bug.cgi?id=13596

Reported-by: dvice_null@yahoo.com

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-24 18:34:39 +01:00
Ralf Baechle
ab7f6f3010 MIPS: MIPSsim: Fix build error if MSC01E_INT_BASE is undefined.
This fixes kernel.org bugzilla 13595, see
http://bugzilla.kernel.org/show_bug.cgi?id=13595

Reported-by: dvice_null@yahoo.com

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-24 18:34:39 +01:00
Ralf Baechle
44eeab6741 MIPS: Hibernation: Remove SMP TLB and cacheflushing code.
We can't perform any flushes on SMP from swsusp_arch_resume because
interrupts are disabled.  A cross-CPU flush is unnecessary anyway
because all but the local CPU have already been disabled.  A local
flush is not needed either because we didn't change any mappings.  So
just delete the code.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-24 18:34:39 +01:00
Ralf Baechle
631330f584 MIPS: Build fix - include <linux/smp.h> into all smp_processor_id() users.
Some of the were relying into smp.h being dragged in by another header
which of course is fragile.  <asm/cpu-info.h> uses smp_processor_id()
only in macros and including smp.h there leads to an include loop, so
don't change cpu-info.h.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-24 18:34:39 +01:00
Ralf Baechle
0ca5921e79 MIPS: bug.h Build fix - include <linux/compiler.h>.
In the past this file somehow used to be dragged in.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-24 18:34:38 +01:00
Linus Torvalds
d06063cc22 Move FAULT_FLAG_xyz into handle_mm_fault() callers
This allows the callers to now pass down the full set of FAULT_FLAG_xyz
flags to handle_mm_fault().  All callers have been (mechanically)
converted to the new calling convention, there's almost certainly room
for architectures to clean up their code and then add FAULT_FLAG_RETRY
when that support is added.

Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-06-21 13:08:22 -07:00
Matthew Wilcox
a6c140969b Delete pcibios_select_root
This function was only used by pci_claim_resource(), and the last commit
deleted that use.

Signed-off-by: Matthew Wilcox <willy@linux.intel.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-06-17 14:04:42 -07:00
Wu Zhangjin
363c55cae5 MIPS: Add hibernation support
[Ralf: SMP support requires CPU hotplugging which MIPS currently doesn't
support.  As implemented in this patch cache and tlb flushing will also be
invoked with interrupts disabled so smp_call_function() will blow up in
charming ways.  So limit to !SMP.]

Reviewed-by: Pavel Machek <pavel@ucw.cz>
Reviewed-by: Yan Hua <yanh@lemote.com>
Reviewed-by: Arnaud Patard <apatard@mandriva.com>
Reviewed-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Wu Zhangjin <wuzj@lemote.com>
Signed-off-by: Hu Hongbing <huhb@lemote.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:31 +01:00
David Daney
4bb1a1089e MIPS: Move Cavium CP0 hwrena impl bits to cpu-feature-overrides.h
We had an ugly #ifdef for Cavium Octeon hwrena bits in traps.c, remove
it to mach-cavium-octeon/cpu-feature-overrides.h

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:31 +01:00
David Daney
fbeda19f82 MIPS: Allow CPU specific overriding of CP0 hwrena impl bits.
Some CPUs have implementation dependent rdhwr registers.  Allow them
to be enabled on a per CPU basis.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:31 +01:00
David Daney
9cffd154cf MIPS: Kconfig Add SYS_SUPPORTS_HUGETLBFS and enable it for some systems.
Add new kconfig variables SYS_SUPPORTS_HUGETLBFS and
CPU_SUPPORTS_HUGEPAGES.  They are enabled for systems that are known
to support huge pages.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:31 +01:00
David Daney
fd062c847a MIPS: TLB support for hugetlbfs.
The TLB handlers need to check for huge pages and give them special
handling.  Huge pages consist of two contiguous sub-pages of physical
memory.

* Loading entrylo0 and entrylo1 need to be handled specially.

* The page mask must be set for huge pages and then restored after
  writing the TLB entries.

* The PTE for huge pages resides in the PMD, we halt traversal of the
  tables there.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:30 +01:00
David Daney
dd7943920b MIPS: Add hugetlbfs page defines.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:30 +01:00
David Daney
50a41ff292 MIPS: Add support files for hugetlbfs.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:30 +01:00
David Daney
bd1437e49d MIPS: Remove unused parameters from iPTE_LW.
The l parameter to iPTE_LW() is unused. Remove it and from some of its
callers as well.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:30 +01:00
David Daney
38295fb2a0 MIPS: Export erratum function needed by octeon-ethernet driver.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:29 +01:00
David Daney
f1f1f5902b MIPS: Cavium-Octeon: Add more chip specific feature tests.
The octeon-ethernet driver needs to check for additional chip specific
features, we add them to the octeon_has_feature() framework.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:29 +01:00
David Daney
2b1b62e841 MIPS: Cavium-Octeon: Add more board type constants.
The bootloader now uses additional board type constants.  The
octeon-ethernet driver needs some of the new values.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:29 +01:00
David Daney
3e903bd9b1 MIPS: Export cvmx_sysinfo_get needed by octeon-ethernet driver.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:29 +01:00
David Daney
6fa044ab8a MIPS: Add named alloc functions to OCTEON boot monitor memory allocator.
The various Octeon ethernet drivers use these new functions.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:29 +01:00
Manuel Lauss
ce65cc8fe2 MIPS: Alchemy: devboards: Convert to gpio calls.
Replace a few open-coded GPIO register accesses with gpio calls.

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:29 +01:00
Manuel Lauss
b6c9f10517 MIPS: Alchemy: xxs1500: use linux gpio api.
Replace a few GPIO register accesses in the board init code with calls to
the gpio api.

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:29 +01:00
Manuel Lauss
bb706b28bb MIPS: Alchemy: MTX-1: Use linux gpio api.
Replace a few GPIO register accesses in the board init code with calls
to the gpio api.

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:28 +01:00
Manuel Lauss
51e02b02e6 MIPS: Alchemy: Rewrite GPIO support.
The current in-kernel Alchemy GPIO support is far too inflexible for
all my use cases.  To address this, the following changes are made:

* create generic functions which deal with manipulating the on-chip
  GPIO1/2 blocks.  Such functions are universally useful.
* Macros for GPIO2 shared interrupt management and block control.
* support for both built-in CONFIG_GPIOLIB and fast, inlined GPIO macros.

  If CONFIG_GPIOLIB is not enabled, provide linux gpio framework
  compatibility by directly inlining the GPIO1/2 functions.  GPIO access
  is limited to on-chip ones and they can be accessed as documented in
  the datasheets (GPIO0-31 and 200-215).

  If CONFIG_GPIOLIB is selected, two (2) gpio_chip-s, one for GPIO1 and
  one for GPIO2, are registered.  GPIOs can still be accessed by using
  the numberspace established in the databooks.

  However this is not yet flexible enough for my uses:  My Alchemy
  systems have a documented "external" gpio interface (fixed, different
  numberspace) and can support a variety of baseboards, some of which
  are equipped with I2C gpio expanders.  I want to be able to provide
  the default 16 GPIOs of the CPU board numbered as 0..15 and also
  support gpio expanders, if present, starting as gpio16.

  To achieve this, a new Kconfig symbol for Alchemy is introduced,
  CONFIG_ALCHEMY_GPIO_INDIRECT, which boards can enable to signal
  that they don't want the Alchemy numberspace exposed to the outside
  world, but instead want to provide their own.  Boards are now respon-
  sible for providing the linux gpio interface glue code (either in a
  custom gpio.h header (in board include directory) or with gpio_chips).

  To make the board-specific inlined gpio functions work, the MIPS
  Makefile must be changed so that the mach-au1x00/gpio.h header is
  included _after_ the board headers, by moving the inclusion of
  the mach-au1x00/ to the end of the header list.

  See arch/mips/include/asm/mach-au1x00/gpio.h for more info.

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Acked-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:28 +01:00
Manuel Lauss
eeb09e6545 MIPS: Alchemy: Remove unused au1000_gpio.h header
Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:28 +01:00
Matthieu Castet
f203b7cacb MIPS: BCM47xx: Fix gpio_direction_output
gpio_direction_output should also set an output value according to the API.

Signed-off-by: Matthieu CASTET <castet.matthieu@free.fr> 
Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:28 +01:00
Ralf Baechle
cc906f8e23 MIPS: ioctl.h: Cleanup.
o Rewrite to use <asm-generic/ioctl.h>.  Cuts down the file from 40 to
   16 lines.
 o Delete _IOC_VOID, _IOC_OUT, _IOC_IN and _IOC_INOUT.  They were added
   for 2.1.14 but I was not able to find any user - not even historical
   ones.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:28 +01:00
Atsushi Nemoto
923e381900 MIPS: TXx9: Add TX4939 RNG support
Add platform support for RNG of TX4939 SoC.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:27 +01:00
Atsushi Nemoto
c3b28ae260 MIPS: TXx9: Add SRAMC support
Add a sysdev to access SRAM in TXx9 SoCs via sysfs.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:27 +01:00
Imre Kaloz
05f94eebd5 MIPS: Sibyte: Remove standalone kernel support
CFE is the only supported and used bootloader on the SiByte boards,
the standalone kernel support has been never used outside Broadcom.
Remove it and make the kernel use CFE by default.

Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:27 +01:00
Imre Kaloz
435f81f4a2 MIPS: Sibyte: Remove simulator option
This patch removes the SiByte simulation Kconfig option, which only modified
a printk.

Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:27 +01:00
Florian Fainelli
d36773e53f MIPS: RB532: Check irq number when handling GPIO interrupts
This patch makes sure that we are not going to clear
or change the interrupt status of a GPIO interrupt
superior to 13 as this is the maximum number of GPIO
interrupt source (p.232 of the RC32434 reference manual).

Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:27 +01:00
Florian Fainelli
1c99dac8bf MIPS: RB532: Cleanup cpu-features-overrides
Remove commented out definitions.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:26 +01:00
David Daney
faed5288af MIPS: Remove dead case label.
CPU_CAVIUM_OCTEON is mips_r2 which is handled before the switch.  This
label in the switch statement is dead code, so we remove it.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Reviewed by: David VomLehn <dvomlehn@cisco.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:26 +01:00
David Daney
9e290a19f2 MIPS: Remove execution hazard barriers for Octeon.
The Octeon has no execution hazards, so we can remove them and save an
instruction per TLB handler invocation.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Reviewed by: David VomLehn <dvomlehn@cisco.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:26 +01:00