start using the SRAM driver for some omaps, and update the
defconfig.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUGzhLAAoJEBvUPslcq6VzHcMQAK/WsTqmMgZ6ydOQGzOuyELi
wLUrSdIHmw6vRYAdgWlXHS9X/F3avqS3tDXjUgW7801prbVn1MvSZ+Re3e862Md9
GdDpB2Q1fV6J9BFXY8nENkHIf7S86Nnsa5yGh6i6IIPHizmb2jf2KrRRSrsrRVA4
00PhmTlLaQb4Xuo4WG2PkOF/g10/vBqboRsG8Jhn9QTlBUYByYqNJJ3tKw9gHccr
UdYe94XjX6HLfenSv/FeWobk1QMnNJdjXmj4obgZtauKku6ZUOA5y41spirry8Rg
G9d+MJByrwG/2O2Vq71Ap0HSlGN00odlFco1FIUw8K3d5RVYD2VLDE+ROJiFBSKg
yavCrmZj7aTh+fMZuvprFKo0PBMlqZMCCsokz51MWxql6Unt9eXKbAey40KtAoo6
Y6Nq4ijdirJTWcdnKjk3dg4Mz6avHRSP+8YqndxNnnI1WS3++aI/GJNT5sCYuDG5
DezFkKET3DvIpKxHByh+n+H6P8NV3MPQ6vvV2qZAv3mvnDdA109Rgb2XamHKgf6z
dP76dA05K7/XFCRjZwbSAYJYAA3nU51fPkH1lO79oBwuP8OCqcBo6CAk22lXZupW
Dkkk+LWhYRAEvExHVEUs6raGJErOrFLtWF3wLkWVjSWZDC+Pb5psHqzGw9ck2Po1
aI+/ZyHh2P8Nl7X1G7kZ
=iau9
-----END PGP SIGNATURE-----
Merge tag 'soc-part2-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
Pull "part 2 of omap SoC changes" from Tony Lindgren:
Few hwmod changes to support upcoming 8250 driver with DMA,
start using the SRAM driver for some omaps, and update the
defconfig.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'soc-part2-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP4+: Remove static iotable mappings for SRAM
ARM: OMAP4+: Move SRAM data to DT
ARM: AM335x: Get rid of unused sram init function
ARM: omap2plus_defconfig: Enable some display features
ARM: omap2plus_defconfig: Enable battery and reset drivers
ARM: omap2plus_defconfig: Add support for distros with systemd
ARM: omap2plus_defconfig: Add cpufreq to defconfig
ARM: omap2plus_defconfig: Shrink with savedefconfig
ARM: OMAP3: Use manual idle for UARTs because of DMA errata
ARM: OMAP2+: Add hwmod flag for HWMOD_RECONFIG_IO_CHAIN
Merge "ARM: BCM: Broadcom BCM63138 support" from Florian Fainelli:
This patchset adds very minimal support for the BCM63138 SoC which is
a xDSL SoC using a dual Cortex A9 CPU complex.
* tag 'bcm63138-v4' of http://github.com/brcm/linux:
MAINTAINERS: add entry for the Broadcom BCM63xx ARM SoCs
ARM: BCM63XX: add BCM963138DVT Reference platform DTS
ARM: BCM63XX: add BCM63138 minimal Device Tree
ARM: BCM63XX: add low-level UART debug support
ARM: BCM63XX: add basic support for the Broadcom BCM63138 DSL SoC
Conflicts:
arch/arm/Kconfig.debug
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* r8a7740: Fix documentation error coppied from elsewhere
* r8a7794: Reserve memory for CMA in a manner consistent to
other R-Car Gen2 SoCs
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUG61hAAoJENfPZGlqN0++YrEP/2AUMZCOUlKOz71JMS9d26vD
g64wXv8SEezY+RwBnxO2CNNPGUQf+3RjGNIyEhE62PbF7y6RcDz6sFxhR7FKrnf4
aDFC/fyh2jot3lsPmEv8fBH94FkmAao/dyO6nAlaJ64ACGDoApecWlL3KFBG6i7a
QRB3e+tRetGEHQsdlwLrap8SJN0YigkjFKorOVHEAHnQlNnULCRYcGgJo742jGyr
6IEiZUGn5OOWWRtiTWs1oWQbMsnbHmgG4l6/51NKkuD/uoxq7gMbBiHu9ht5npmo
e5zPQ+1ILA9hI43Mk52vfilNXdBn7urTjc6CtROXWBer35smJ5kpxj5WSKpT7jTN
MXENqilQiYeTbP5GR3p96p4JiL2U3Zd+frxfsPOMgyfvTGEdYFULfuXgblgwEGv2
RC/8AB8lfcnwPnkI1C21GR2Zbt7bw8ytJD9iQoTb1GEqyVMd/Oxrp0S+/Zk9EoVW
w+3fCRJrBQVmTDi9XArqt5IgpjloZndfkwVX6J45/KJu4/gFCv1AKYSw7bD/rNrD
cZzDYtkj9DbO125gDDfyJo+jMOMJGVUnHv9XSLgBpUbaEKfa9oh2hpwPoM0C/OS5
KHMISR2rFu4vVteLlANLODSFoprM1Xyd4NDFqp5bdwN7RoMZFLOHHwlzmMXn/Xc8
lladCk6BwpEkOUYYriG3
=wfDI
-----END PGP SIGNATURE-----
Merge tag 'renesas-soc5-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
Pull "Fifth Round of Renesas ARM Based SoC Soc Updates for v3.18" from Simon Horman:
* r8a7740: Fix documentation error copied from elsewhere
* r8a7794: Reserve memory for CMA in a manner consistent to
other R-Car Gen2 SoCs
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'renesas-soc5-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7740 legacy: Fix copied bug in comment
ARM: shmobile: r8a7794: Reserve memory as other R-Car Gen2 SoCs
the primary change here gets its address information from DT rather than
iomap.h. This removes one more user of iomap.h, and will help allow the
code to move to a location that can be shared between arch/arm and
arch/arm64.
An unused header file was also removed.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUGxmUAAoJEMzrak5tbycxh8gP/AraovjYUwxHfFDkRgRn/Ukb
t8PRy/mieHwypO86Rseu4x5P+OWO3MFMYLfqFpJZAYugwq7hgB6dCCcFuezqDP0k
HVBBQN1wu8XDpjJd260EQmzjx8mqW+omMmeWZcZSMChnqPsntVpCmbWf4dlGoAcY
qgGfiNVZ7QWsS7ROjGD9JI0SmkYdfoXWtPX6r0z93sn3SM4lrJeIs/RGYKfEaQb0
JXvJChj/K59Z8ejUjM5pI2CkC0Y23ftl5BH6sJk9yiFRA09UDahdUJiO1wcM0TgK
oukVFOapGyGscFrN/bZq79RPde1P0GnbllcT0aOV5PWr4R6HGEArxrsVm7UoC+L3
3J3OwpG5EokCOh7Agt81ExTP6uaohWZKC4WS8l247qbDXhdxIXscmTk9Y3Fey//x
UM044kprNgUaRiQ/fFFx8W+6V3dHthCD6TslNCN8E0s1yjqgw8lLyuW0YqaO+CJe
q3+d8Twf2d8GUwOPmh2hSYh1kGt47YNQvrQ+bkdb9FFOtkrrYZykPSDI71H/IpIR
wrmHiueQV1zu6f4KRCgYgg5SQj/SI9rncoI1innarw+JszSK5Pn8fKp+z9mTRDML
oaSCSKc9UNMVAMfex1p1GYgxuVbCQex6VHFTRXke99CJA7nedRzhB6v8wk7ICdXP
pb3AeTLB4R1rr7Ull1mt
=BeSe
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-3.18-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc
Pull "ARM: tegra: core SoC code changes for 3.18" from Stephen Warren:
the primary change here gets its address information from DT rather than
iomap.h. This removes one more user of iomap.h, and will help allow the
code to move to a location that can be shared between arch/arm and
arch/arm64.
An unused header file was also removed.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'tegra-for-3.18-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra: remove unused tegra_emc.h
ARM: tegra: Initialize flow controller from DT
of: Add NVIDIA Tegra flow controller bindings
This patch adds the basic machine file for the MesonX SoCs. Only Meson6
is populated.
Signed-off-by: Carlo Caione <carlo@caione.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add the UART definitions needed to support earlyprintk for MesonX SoCs
on UARTAO.
Signed-off-by: Carlo Caione <carlo@caione.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Add initial devicetree support for i.MX1
- Support GPT per clock source from OSC for i.MX6
- A couple of parent selection corrections for i.MX6SL clock driver
- Support more chip revision for i.MX6
- Convert pr_warning to pr_warn
- Add exclusive gate clock support
- Add BYPASS support for i.MX6 PLL clocks
- Update i.MX6 clock tree for audio use case
- A couple of VF610 clock driver updates
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJUF672AAoJEFBXWFqHsHzOTXQIAJ0ZTXtzQsJ3gLFU+CwRMm2F
hIzFDNOsRkEYpJaa6AkweBmLyUUdePn9rUVRzCi4P9Ux5uCSU6sd3CPHOykOCrV4
xGXk+hL47IpPNGP1tZ4NU7bVBz4BvrIkLRXBxlO+YZ2ZKf+k8Ma166c3iwYFqpDD
8Fd7SQrKleZiXXDgz6y8SRCsOre3HmmjeJBBHhKuegSRscyh2cYfduBsmr6xTojR
Jzcega1pprb1ojxflMVLHcGRquyYVHaoH65mD4leDhSWa93MZFCOAFCl27qsZNs5
gTlaayqq8ws8aFOXi9OmONSjL+ZBMkf0Jk/QGOo5cLCUKYYv10KK2LXFeBOpg8A=
=yLWI
-----END PGP SIGNATURE-----
Merge tag 'imx-soc-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc
Merge "ARM: imx: SoC updates for 3.18" from Shawn Guo:
The i.MX SoC updates for 3.18:
- Add initial devicetree support for i.MX1
- Support GPT per clock source from OSC for i.MX6
- A couple of parent selection corrections for i.MX6SL clock driver
- Support more chip revision for i.MX6
- Convert pr_warning to pr_warn
- Add exclusive gate clock support
- Add BYPASS support for i.MX6 PLL clocks
- Update i.MX6 clock tree for audio use case
- A couple of VF610 clock driver updates
* tag 'imx-soc-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (30 commits)
ARM: imx_v6_v7_defconfig updates
ARM: imx_v4_v5_defconfig: Select CONFIG_IMX_WEIM
arm: mach-imx: Convert pr_warning to pr_warn
ARM: imx: source gpt per clk from OSC for system timer
ARM: imx: add gpt_3m clk for i.mx6qdl
ARM: imx: fix register offset of pll7_usb_host gate clock
ARM: clk-imx6sl: refine clock tree for SSI
ARM: imx: remove ENABLE and BYPASS bits from clk-pllv3 driver
ARM: imx6sx: add BYPASS support for PLL clocks
ARM: imx6sl: add BYPASS support for PLL clocks
ARM: imx6q: add BYPASS support for PLL clocks
ARM: imx: add an exclusive gate clock type
ARM: clk-imx6q: refine clock tree for SSI
ARM: clk-imx6q: refine clock tree for ASRC
ARM: clk-imx6sl: correct the pxp and epdc axi clock selections
ARM: clk-imx6q: refine clock tree for ESAI
ARM: clk-imx6sl: Select appropriate parents for LCDIF clocks
ARM: clk-imx6sl: Remove csi_lcdif_sels[]
ARM: imx: clk-vf610: Add USBPHY clocks
ARM: imx: add cpufreq support for i.mx6sx
...
Signed-off-by: Olof Johansson <olof@lixom.net>
When compiling with "ARCH=arm" and "allmodconfig",
with commit: 9cdc99919a [2/7] ARM: hisi: enable MCPM implementation
we will get:
/tmp/cc6DjYjT.s: Assembler messages:
/tmp/cc6DjYjT.s:63: Error: selected processor does not support ARM mode `ubfx r1,r0,#8,#8'
/tmp/cc6DjYjT.s:761: Error: selected processor does not support ARM mode `isb '
/tmp/cc6DjYjT.s:762: Error: selected processor does not support ARM mode `dsb '
/tmp/cc6DjYjT.s:769: Error: selected processor does not support ARM mode `isb '
/tmp/cc6DjYjT.s:775: Error: selected processor does not support ARM mode `isb '
/tmp/cc6DjYjT.s:776: Error: selected processor does not support ARM mode `dsb '
/tmp/cc6DjYjT.s:795: Error: selected processor does not support ARM mode `isb '
/tmp/cc6DjYjT.s:801: Error: selected processor does not support ARM mode `isb '
/tmp/cc6DjYjT.s:802: Error: selected processor does not support ARM mode `dsb '
Fix platmcpm compilation when ARMv6 is selected.
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
HIP04 was added out of order, but so was the previous HISI debug uart
support as well. Minor reshuffling of order.
Signed-off-by: Olof Johansson <olof@lixom.net>
- PM changes to make the code easier to use on newer SoCs
- PM changes for newer SoCs suspend and resume and wake-up events
- Minor clean-up to remove dead Kconfig options
Note that these have a dependency to the fixes-v3.18-not-urgent
tag and is based on a commit in that series.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUEhKGAAoJEBvUPslcq6VzURoP/3tM1iOFzQ83xe0ijEnHuUEz
To5DF1AgJ/l8a6H9FV9xDTn7SXjV8Fts0MrPwveGnKRUMmZfrUBedvWGM9NyyWm5
L7IJKHvSc7FAj7ee5crNobCYTrQ9THUlr8X1mLILFl5mTh2pDnm4ZRscHy+OxN0+
w97d/T5MrFhoCa8LXo8nGm7jROvayp+E0VTxjFdU07VKJK8xjd++M0B5U3pXsqCC
8VabNDt8VBK/SVCOKYn3tnNop1/9t9nSWfN18OAEaIS6rn5ZaQxXETKxyRWgjTvn
OVEgsazFiPVm87H3O6cj0BizOSXG2gMfBTECZwVPtavyQR2lb/YljHUQ5Z9/T4v9
x+nOWFxqVAr8OM1kKcatSMrZymY4AG5NdOmOgrAqKoQzWGGKhT3LcNz3Ecja25vX
ZWGYsJl6hbF4PPaCgKe8KGRISLuv1g1N4TI8ztsxELRzhClxhuaERt7TkdQRLGrH
emKSFP8Kkn6yrQy/RirOaXnwPWJRzuMrgpLuwDTKY6vY07MGk+nHkzF+2itKkvLB
CG/Tw29jUi9gnOU9QwjkpBiJxsHlgcO/XzSTGN89p6EjVylyqdCqkpO3MCfjPV7Q
kPap33Zx5SvxMMMSXRDKrrez533RfxBeTXkgT1O0fnR0r4fWYoc5+zL8Y02g10Wt
tZ4gZRYP68IuxzfPUAgJ
=LW8C
-----END PGP SIGNATURE-----
Merge tag 'soc-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
SoC related changes for omaps for v3.18 merge window:
- PM changes to make the code easier to use on newer SoCs
- PM changes for newer SoCs suspend and resume and wake-up events
- Minor clean-up to remove dead Kconfig options
Note that these have a dependency to the fixes-v3.18-not-urgent
tag and is based on a commit in that series.
* tag 'soc-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (514 commits)
ARM: OMAP5+: Reuse OMAP4 PM code for OMAP5 and DRA7
ARM: dts: OMAP3+: Add PRM interrupt
ARM: omap: Remove stray ARCH_HAS_OPP references
ARM: DRA7: Add hook in SoC initcalls to enable pm initialization
ARM: OMAP5: Add hook in SoC initcalls to enable pm initialization
ARM: OMAP5 / DRA7: Enable CPU RET on suspend
ARM: OMAP5 / DRA7: PM: Provide a dummy startup function for CPU hotplug
ARM: OMAP5 / DRA7: PM: Avoid all SAR saves
ARM: OMAP5 / DRA7: PM: Enable Mercury retention mode on CPUx powerdomains
ARM: OMAP5 / DRA7: PM / wakeupgen: Enables ES2 PM mode by default
ARM: OMAP5 / DRA7: PM: Set MPUSS-EMIF clock-domain static dependency
ARM: OMAP5 / DRA7: PM: Update CPU context register offset
ARM: AM437x: use pdata quirks for pinctrl information
ARM: DRA7: use pdata quirks for pinctrl information
ARM: OMAP5: use pdata quirks for pinctrl information
ARM: OMAP4+: PM: Use only valid low power state for CPU hotplug
ARM: OMAP4+: PM: use only valid low power state for suspend
ARM: OMAP4+: PM: Make logic state programmable
ARM: OMAP2+: powerdomain: introduce logic for finding valid power domain
ARM: OMAP2+: powerdomain: pwrdm_for_each_clkdm iterate only valid clkdms
...
Currently, devices for SSP ports 1, 2 and 3 are registered as compatible
devices to pxa27x-ssp. While the actual IP core is comparable, there are
some subtle differences which users of the SSP ports address by looking at
the 'type' field.
By registering devices of type 'pxa27x-ssp', this 'type' field is
incorrectly set to PXA27x_SSP which confuses the users.
To fix this, provide specific ssp port plaform devices which use
'pxa3xx-ssp' as driver name, an instantiate them from pxa3xx.c.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Provide an explicit match string for PXA3xx SSP ports.
Without this match string, SSP0/SSP1/SSP2 in PXA3xxx will be consided as
PXA27x SSP Port.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
In order to handle errata I688, a page of sram was reserved by doing a
static iotable map. Now that we use gen_pool to manage sram, we can
completely remove all of these static mappings and use gen_pool_alloc()
to get the one page of sram space needed to implement errata I688.
omap_bus_sync will be NOP until SRAM initialization happens.
Suggested-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Use drivers/misc/sram.c driver to manage SRAM on all DT only
OMAP platforms (am33xx, am43xx, omap4 and omap5) instead of
the existing private plat-omap/sram.c
Address and size related data is removed from mach-omap2/sram.c
and now passed to drivers/misc/sram.c from DT.
Users can hence use general purpose allocator apis instead of
OMAP private ones to manage and use SRAM.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Now that we have panel support for DT based booting,
let's make it usable and enable most things as modules.
Note that omap3 boards need also the ads7847 module for
the panel that we're now changing to a loadable module.
And n900 seems to require setting the brightness via
sysfs for acx565akm/brightness after modprobe of
panel_sony_acx565akm and omapfb.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Since many omaps run on battery, we should have the battery
drivers enabled. Let's also enable the reset driver.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Some distros are now using systemd, so let's enable most of
what's recommended at:
http://cgit.freedesktop.org/systemd/systemd/tree/README
Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Note that we can now use the CONFIG_GENERIC_CPUFREQ_CPU0,
so let's only enable that. Let's use CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND
as suggested by Nishant.
And also let's enable thermal as explained by Nishant Menon:
Many TI SoCs using Highest frequency is not really too nice of an idea for
long periods of time. And not everything is upstream to support things
optimially - example avs class 0, 1.5 ABB consolidation with cpufreq etc..
We definitely need thermal enabled as well for device safety needs.
[tony@atomide.com: updated per Nishant's suggestions]
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
In sprz318f.pdf "Usage Note 2.7" says that UARTs cannot acknowledge
idle requests in smartidle mode when configured for DMA operations.
This prevents L4 from going idle. So let's use manual idle mode
instead.
Otherwise systems using Sebastian's 8250 patches with DMA will
never enter deeper idle states because of the errata above.
Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Commit cc824534d4 ("ARM: OMAP2+: hwmod: Rearm wake-up interrupts
for DT when MUSB is idled") fixed issues with hung UART wake-up
events by calling _reconfigure_io_chain() when MUSB is connected
or disconnected.
As pointed out by Paul Walmsley, we may need to also call
_reconfigure_io_chain() in other cases, so it should be a separate
flag. Let's add HWMOD_RECONFIG_IO_CHAIN as suggested by Paul.
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add a very minimalistic BCM63138 Device Tree include file which
describes the BCM63138 SoC with only the basic set of required
peripherals:
- Cortex A9 CPUs
- ARM GIC
- ARM SCU
- PL310 Level-2 cache controller
- ARM TWD & Global timers
- ARM TWD watchdog
- legacy MIPS bus (UBUS)
- BCM6345-style UARTs (disabled by default)
Since the PL310 L2 cache controller does not come out of reset with
correct default values, we need to override the 'cache-sets' and
'cache-size' properties to get its geometry right.
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Broadcom BCM63xx DSL SoCs have a different UART implementation for which
we need specially crafted low-level debug assembly code to support. Add
support for this using the standard definitions provided in
include/linux/serial_bcm63xx.h (shared with their MIPS counterparts).
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This patch adds basic support for the Broadcom BCM63138 DSL SoC which is
using a dual-core Cortex A9 system. Add the very minimum required code
boot Linux on this SoC.
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
The corresponding bug in pm-sh7372.c was fixed in commit
70fe7b2467 ("ARM: shmobile: Do not access sh7372 A4S domain
internals directly").
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
AUX setting has no effect that's why remove it.
Warning log:
L2C: platform provided aux values match the hardware, so
have no effect. Please remove them.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Match the naming pattern of all other SMP ops and rename
zynq_platform_cpu_die --> zynq_cpu_die.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The hotplug code contains only a single function, which is an SMP
function. Move that to platsmp.c where all other SMP runctions reside.
That allows removing hotplug.c and declaring the cpu_die function
static.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Avoid races and add synchronisation between the arch specific
kill and die routines.
The same synchronisation issue was fixed on IMX platform
by this commit:
"ARM: imx: fix sync issue between imx_cpu_die and imx_cpu_kill"
(sha1: 2f3edfd7e2)
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
As there is no Power management unit on this board, it is not possible to power
down a core, just WFI is allowed. There is no point to invalidate the cache and
exit coherency.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-and-tested-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The DDR controller can detect idle periods and leverage low power
features clock stop. When new requests occur, the DDRC resumes
normal operation.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add the DDR controller to the Zynq devicetree.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Other R-Car Gen2 SoCs such as r8a7790 and r8a7791 reserve
the top 256 MiB of memory for use with CMA. Adjust the
board-less r8a7794 code to do the same.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The rtc isl1208 driver is used by mx6 nitrogen board, so let's enable it by
default.
The fsl sai driver is used by the vf610-twr board, so let's enable it by
default.
simple-audio-card driver is used by the vf610-twr board, so let's enable it by
default.
Generated this patch by doing:
- make imx_v6_v7_defconfig
- make menuconfig and manually select options
- make savedefconfig
- cp defconfig arch/arm/configs/imx_v6_v7_defconfig
,which results in some additional cleanups.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The imx weim driver is used by some mx27/mx1 boards, so let's enable it by
default.
Generated this patch by doing:
- make imx_v4_v5_defconfig
- make menuconfig and manually select CONFIG_IMX_WEIM
- make savedefconfig
- cp defconfig arch/arm/configs/imx_v4_v5_defconfig
,which results in some additional cleanups.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
On i.MX6Q TO > 1.0, i.MX6DL and i.MX6SX, gpt per clock
can be from OSC instead of ipg_per, as ipg_per's rate
may be scaled when system enter low bus mode, to keep
system timer NOT drift, better to make gpt per clock
at fixed rate, here add support for gpt per clock to
be from OSC which is at fixed rate always.
There are some difference on this implementation of
gpt per clock source, see below for details:
i.MX6Q TO > 1.0: GPT_CR_CLKSRC, b'101 selects fix clock
of OSC / 8 for gpt per clk;
i.MX6DL and i.MX6SX: GPT_CR_CLKSRC, b'101 selects OSC
for gpt per clk, and we must enable GPT_CR_24MEM to
enable OSC clk source for gpt per, GPT_PR_PRESCALER24M
is for pre-scaling of this OSC clk, here set it to 8
to make gpt per clk is 3MHz;
i.MX6SL: ipg_per can be from OSC directly, so no need to
implement this new clk source for gpt per.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Add gpt_3m clock for i.mx6qdl, as gpt can source clock
from OSC, some i.MX6 series SOCs has fixed divider of
8 for gpt clock, so here add a fix clk of gpt_3m.
i.MX6Q TO1.0 has no gpt_3m option, so force it to be
from ipg_per.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
There is a copy&paste error on register offset of pll7_usb_host gate
clock introduced by i.MX6 PLL bypass support patches. The error breaks
the ENET function, because it overwrites the pll6_enet gate bit.
Correct the offset for all i.MX6 clock drivers.
Thanks to Fugang Duan <B38611@freescale.com> for spotting the error.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Since ENABLE and BYPASS bits of PLLs are now implemented as separate
gate and mux clocks by clock drivers, the code handling these two bits
can be removed from clk-pllv3 driver.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This is the same change for imx6sx clock driver as "ARM: imx6q: add BYPASS
support for PLL clocks" for imx6q. The difference is that only anaclk1
is available on imx6sx.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
