Commit Graph

812 Commits

Author SHA1 Message Date
Rob Herring
fae2b89ab1 ARM: l2x0: add empty l2x0_of_init
Add empty version of l2x0_of_init for when CONFIG_CACHE_L2X0 is not selected.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Barry Song <21cnbao@gmail.com>
Reviewed-by: Shawn Guo <shawn.guo@linaro.org>
2011-10-31 14:13:57 +01:00
Arnd Bergmann
09fa31a322 Merge branch 'dt/gic' into highbank/soc
Conflicts:
	arch/arm/Kconfig
2011-10-31 14:11:34 +01:00
Rob Herring
f37a53cc5d ARM: gic: fix irq_alloc_descs handling for sparse irq
Commit "ARM: gic: add irq_domain support" (b49b6ff) breaks SPARSE_IRQ
on platforms with GIC. When SPARSE_IRQ is enabled, all NR_IRQS or
mach_desc->nr_irqs will be allocated by arch_probe_nr_irqs(). This caused
irq_alloc_descs to allocate irq_descs after the pre-allocated space.

Make irq_alloc_descs search for an exact irq range and assume it has
been pre-allocated on failure. For DT probing dynamic allocation is used.
DT enabled platforms should set their nr_irqs to NR_IRQ_LEGACY and have all
irq_chips allocate their irq_descs with irq_alloc_descs if SPARSE_IRQ is
enabled.

gic_init irq_start param is changed to be signed with negative meaning do
dynamic Linux irq assigment.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2011-10-31 14:03:27 +01:00
Rob Herring
b3f7ed0324 ARM: gic: add OF based initialization
This adds ARM gic interrupt controller initialization using device tree
data.

The initialization function is intended to be called by of_irq_init
function like this:

const static struct of_device_id irq_match[] = {
	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
	{}
};

static void __init init_irqs(void)
{
	of_irq_init(irq_match);
}

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Reviewed-by: Jamie Iles <jamie@jamieiles.com>
Tested-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
2011-10-31 14:03:26 +01:00
Rob Herring
4294f8baaf ARM: gic: add irq_domain support
Convert the gic interrupt controller to use irq domains in preparation
for device-tree binding and MULTI_IRQ. This allows for translation between
GIC interrupt IDs and Linux irq numbers.

The meaning of irq_offset has changed. It now is just the number of skipped
GIC interrupt IDs for the controller. It will be 16 for primary GIC and 32
for secondary GICs.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Jamie Iles <jamie@jamieiles.com>
Tested-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
2011-10-31 14:03:24 +01:00
Arnd Bergmann
36bc45e219 Merge branches 'depends/rmk/io', 'depends/rmk/l2x0' and 'depends/rmk/gpio' into highbank/soc 2011-10-30 23:26:28 +01:00
Rob Herring
3a82543642 Merge remote-tracking branch 'rmk/devel-stable' into HEAD 2011-10-24 14:02:37 -05:00
Russell King
34471a9168 Merge branch 'ppi-irq-core-for-rmk' of git://github.com/mzyngier/arm-platforms into devel-stable 2011-10-23 14:42:30 +01:00
Marc Zyngier
28af690a28 ARM: gic, local timers: use the request_percpu_irq() interface
This patch remove the hardcoded link between local timers and PPIs,
and convert the PPI users (TWD, MCT and MSM timers) to the new
*_percpu_irq interface. Also some collateral cleanup
(local_timer_ack() is gone, and the interrupt handler is strictly
private to each driver).

PPIs are now useable for more than just the local timers.

Additional testing by David Brown (msm8250 and msm8660) and
Shawn Guo (imx6q).

Cc: David Brown <davidb@codeaurora.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: David Brown <davidb@codeaurora.org>
Tested-by: David Brown <davidb@codeaurora.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2011-10-23 13:32:33 +01:00
Marc Zyngier
292b293cee ARM: gic: consolidate PPI handling
PPI handling is a bit of an odd beast. It uses its own low level
handling code and is hardwired to the local timers (hence lacking
a registration interface).

Instead, switch the low handling to the normal SPI handling code.
PPIs are handled by the handle_percpu_devid_irq flow.

This also allows the removal of some duplicated code.

Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: David Brown <davidb@codeaurora.org>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: David Brown <davidb@codeaurora.org>
Tested-by: David Brown <davidb@codeaurora.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2011-10-23 13:32:29 +01:00
Russell King
cefd3e71ef Merge branch 'mach_memory_h' of git://git.linaro.org/people/nico/linux into devel-stable 2011-10-18 13:40:54 +01:00
Barry Song
91c2ebb90b ARM: 7114/1: cache-l2x0: add resume entry for l2 in secure mode
we save the l2x0 registers at the first initialization, and platform codes
can get them to restore l2x0 status after wakeup.

Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:11:51 +01:00
Rob Herring
8c369264b6 ARM: 7009/1: l2x0: Add OF based initialization
This adds probing for ARM L2x0 cache controllers via device tree. Support
includes the L210, L220, and PL310 controllers. The binding allows setting
up cache RAM latencies and filter addresses (PL310 only).

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Olof Johansson <olof@lixom.net>
Acked-by: Barry Song <21cnbao@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:11:30 +01:00
Jamie Iles
5a567d78c4 ARM: 7115/4: move __exception and friends to asm/exception.h
The definition of __exception_irq_entry for
CONFIG_FUNCTION_GRAPH_TRACER=y needs linux/ftrace.h, but this creates a
circular dependency with it's current home in asm/system.h. Create
asm/exception.h and update all current users.

v4:	- rebase to rmk/for-next
v3:	- remove redundant includes of linux/ftrace.h
v2:	- document the usage restricitions of __exception*

Cc: Zoltan Devai <zdevai@gmail.com>
Signed-off-by: Jamie Iles <jamie@jamieiles.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:02:44 +01:00
Shawn Guo
0af8aa0069 ARM: 7124/1: smp: Add a localtimer handler callable from C code
In order to be able to handle localtimer directly from C code instead of
assembly code, introduce handle_local_timer(), which is modeled after
handle_IRQ().

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:02:44 +01:00
Shawn Guo
0b5a1b95dc ARM: 7123/1: smp: Add an IPI handler callable from C code
In order to be able to handle IPI directly from C code instead of
assembly code, introduce handle_IPI(), which is modeled after handle_IRQ().

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:02:43 +01:00
Will Deacon
d6257288c4 ARM: 7060/1: smp: populate logical CPU mapping during boot
To allow booting Linux on a CPU with physical ID != 0, we need to
provide a mapping from the logical CPU number to the physical CPU
number.

This patch adds such a mapping and populates it during boot.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:02:43 +01:00
Vincent Guittot
c9018aab8e ARM: 7011/1: Add ARM cpu topology definition
The affinity between ARM processors is defined in the MPIDR register.
We can identify which processors are in the same cluster,
and which ones have performance interdependency. We can define the
cpu topology of ARM platform, that is then used by sched_mc and sched_smt.

The default state of sched_mc and sched_smt config is disable.
When enabled, the behavior of the scheduler can be modified with
sched_mc_power_savings and sched_smt_power_savings sysfs interfaces.

Changes since v4 :
*  Remove unnecessary parentheses and blank lines

Changes since v3 :
* Update the format of printk message
* Remove blank line

Changes since v2 :
* Update the commit message and some comments

Changes since v1 :
* Update the commit message
* Add read_cpuid_mpidr in arch/arm/include/asm/cputype.h
* Modify header of arch/arm/kernel/topology.c
* Modify tests and manipulation of MPIDR's bitfields
* Modify the place and dependancy of the config
* Modify Noop functions

Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:02:43 +01:00
Nicolas Pitre
0cdc8b921d ARM: switch from NO_MACH_MEMORY_H to NEED_MACH_MEMORY_H
Given that we want the default to not have any <mach/memory.h> and given
that there are now fewer cases where it is still provided than the cases
where it is not at this point, this makes sense to invert the logic and
just identify the exception cases.

The word "need" instead of "have" was chosen to construct the config
symbol so not to suggest that having a mach/memory.h file is actually
a feature that one should aim for.

Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:53:53 -04:00
Nicolas Pitre
1b9f95f8ad ARM: prepare for removal of a bunch of <mach/memory.h> files
When the CONFIG_NO_MACH_MEMORY_H symbol is selected by a particular
machine class, the machine specific memory.h include file is no longer
used and can be removed.  In that case the equivalent information can
be obtained dynamically at runtime by enabling CONFIG_ARM_PATCH_PHYS_VIRT
or by specifying the physical memory address at kernel configuration time.

If/when all instances of mach/memory.h are removed then this symbol could
be removed.

Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-09-26 10:11:58 -04:00
Will Deacon
df77abcafc ARM: 7099/1: futex: preserve oldval in SMP __futex_atomic_op
The SMP implementation of __futex_atomic_op clobbers oldval with the
status flag from the exclusive store. This causes it to always read as
zero when performing the FUTEX_OP_CMP_* operation.

This patch updates the ARM __futex_atomic_op implementations to take a
tmp argument, allowing us to store the strex status flag without
overwriting the register containing oldval.

Cc: stable@kernel.org
Reported-by: Minho Ban <mhban@samsung.com>
Reviewed-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-09-26 12:36:47 +01:00
Russell King
c825dda905 Merge branch 'for_3_2/for-rmk/arm_cpu_pm' of git://gitorious.org/omap-sw-develoment/linux-omap-dev into devel-stable 2011-09-26 09:36:36 +01:00
Santosh Shilimkar
8fb54284ba ARM: mm: Add strongly ordered descriptor support.
On certain architectures, there might be a need to mark certain
addresses with strongly ordered memory attributes to avoid ordering
issues at the interconnect level.

On OMAP4, the asynchronous bridge buffers can only be drained
with strongly ordered accesses and hence the need to mark the
memory strongly ordered.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Woodruff Richard <r-woodruff2@ti.com>
Tested-by: Vishwanath BS <vishwanath.bs@ti.com>
2011-09-23 12:05:30 +05:30
Colin Cross
254056f3b1 ARM: gic: Use cpu pm notifiers to save gic state
When the cpu is powered down in a low power mode, the gic cpu
interface may be reset, and when the cpu cluster is powered
down, the gic distributor may also be reset.

This patch uses CPU_PM_ENTER and CPU_PM_EXIT notifiers to save
and restore the gic cpu interface registers, and the
CPU_CLUSTER_PM_ENTER and CPU_CLUSTER_PM_EXIT notifiers to save
and restore the gic distributor registers.

Original-author: Gary King <gking@nvidia.com>
Signed-off-by: Colin Cross <ccross@android.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-and-Acked-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Vishwanath BS <vishwanath.bs@ti.com>
2011-09-23 12:05:30 +05:30
Russell King
b0a37dca72 Merge branch 'pm' into devel-stable 2011-09-22 22:39:23 +01:00
Russell King
f70cac8d9c Merge branch 'kprobes-test' of git://git.yxit.co.uk/linux into devel-stable 2011-09-21 08:48:33 +01:00
Russell King
abda1bd5f4 ARM: pm: convert some assembly to C
Convert some of the sleep.S guts to C code, which makes it easier to
use our macros and to add L2 cache handling.  We provide a helper
function, __cpu_suspend_save(), which deals with saving the common
state, setting up for resume, and flushing caches.

The remainder left as assembly code is the saving of the CPU general
purpose registers, and allocating space on the stack to save the CPU
specific registers and resume state.

Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-09-20 23:33:44 +01:00
Russell King
e8ce0eb5e2 ARM: pm: preallocate a page table for suspend/resume
Preallocate a page table and setup an identity mapping for the MMU
enable code.  This means we don't have to "borrow" a page table to
do this, avoiding complexities with L2 cache coherency.

Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-09-20 23:33:36 +01:00
Russell King
4dfa33868d ARM: nommu: fix warning with checksyscalls.sh
CALL    scripts/checksyscalls.sh
<stdin>:46:1: warning: "__IGNORE_migrate_pages" redefined
In file included from <stdin>:2:
arch/arm/include/asm/unistd.h:482:1: warning: this is the location of the previous definition

This is caused because we define __IGNORE_migrate_pages to be 1, but
in the case of nommu, it's defined to be empty.  Fix this by just
defining the __IGNORE_ symbols to be empty.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-09-17 12:50:57 +01:00
Russell King
4722cd7741 Merge branch 'for-rmk' of git://linux-arm.org/linux-2.6-wd into devel-stable
Conflicts:
	arch/arm/mach-imx/mach-cpuimx27.c
2011-09-16 21:45:16 +01:00
Linus Walleij
bac7e6ecf6 ARM: 7080/1: l2x0: make sure I&D are not locked down on init
Fighting unfixed U-Boots and other beasts that may the cache in
a locked-down state when starting the kernel, we make sure to
disable all cache lock-down when initializing the l2x0 so we
are in a known state.

Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Rabin Vincent <rabin.vincent@stericsson.com>
Cc: Adrian Bunk <adrian.bunk@movial.com>
Cc: Rob Herring <robherring2@gmail.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reported-by: Jan Rinze <janrinze@gmail.com>
Tested-by: Robert Marklund <robert.marklund@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-09-07 00:48:03 +01:00
Will Deacon
4fb0d2ea39 Merge branches 'hwbreak', 'perf/updates' and 'perf/system-pmus' into for-rmk 2011-08-31 10:50:37 +01:00
Mark Rutland
0ce47080df ARM: perf: move arm_pmu into <asm/pmu.h>
Currently, struct arm_pmu and related functions are only visible to
{,arch/arm/}/kernel/perf_event.c. This prevents new drivers from using
the framework.

This patch  moves declarations to asm/pmu.h, allowing new PMU drivers
to use the framework.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Jamie Iles <jamie@jamieiles.com>
Reviewed-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2011-08-31 10:50:13 +01:00
Will Deacon
6f26aa05c9 ARM: hw_breakpoint: add support for multiple watchpoints
ARM debug architecture 7.1 mandates that the DFAR is updated on a
watchpoint debug exception to contain the faulting virtual address
of the memory access. This allows us to determine which watchpoints
have fired and therefore report useful information to userspace.

This patch adds support for using the DFAR in the watchpoint handler,
which allows us to support multiple watchpoints on CPUs implementing
the new debug architecture.

Signed-off-by: Will Deacon <will.deacon@arm.com>
2011-08-31 10:42:48 +01:00
Will Deacon
b5d5b8f986 ARM: hw_breakpoint: add initial Cortex-A15 (debug v7.1) support
This patch adds initial support for Cortex-A15 (debug architecture v7.1)
to the hw_breakpoint ARM backend.

Signed-off-by: Will Deacon <will.deacon@arm.com>
2011-08-31 10:42:47 +01:00
Will Deacon
b0e89590f4 ARM: PMU: move CPU PMU platform device handling and init into perf
Once upon a time, OProfile and Perf fought hard over who could play with
the PMU. To stop all hell from breaking loose, pmu.c offered an internal
reserve/release API and took care of parsing PMU platform data passed in
from board support code.

Now that Perf has ingested OProfile, let's move the platform device
handling into the Perf driver and out of the PMU locking code.
Unfortunately, the lock has to remain to prevent Perf being bitten by
out-of-tree modules such as LTTng, which still claim a right to the PMU
when Perf isn't looking.

Acked-by: Jamie Iles <jamie@jamieiles.com>
Reviewed-by: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2011-08-31 10:17:59 +01:00
Nicolas Pitre
96f90c7915 Merge the enabling by default of ARM_PATCH_PHYS_VIRT
Conflicts:
	arch/arm/mach-msm/board-msm7x30.c
2011-08-29 15:29:00 -04:00
Russell King
ad30a2bbdc Merge branch 'atag_offset' of git://git.linaro.org/people/nico/linux into devel-stable 2011-08-23 10:54:51 +01:00
Jon Medhurst
99d1717dd7 ARM: Add init_consistent_dma_size()
This function can be called during boot to increase the size of the consistent
DMA region above it's default value of 2MB. It must be called before the memory
allocator is initialised, i.e. before any core_initcall.

Signed-off-by: Jon Medhurst <tixy@yxit.co.uk>
Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-08-22 12:00:10 +00:00
Nicolas Pitre
af6871683e ARM: remove boot_params from struct machine_desc
Now that there is no more users, we can remove it from the kernel.

Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-08-21 17:15:24 -04:00
Nicolas Pitre
2bb9839e31 ARM: introduce atag_offset to replace boot_params
The boot_params member of the mdesc structure is used to provide a
default physical address for the ATAG list.  Since this value is fixed
at compile time and sometimes based on constants such as ARCH_PHYS_OFFSET,
it gets in the way of runtime PHYS_OFFSET and CONFIG_ARM_PATCH_PHYS_VIRT
usage.

Let's introduce atag_offset which should contains only the relative
offset from PHYS_OFFSET instead of an absolute value, in preparation
to move all instance of boot_params over to it.

Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Tested-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Tested-by: Petr Štetiar <ynezz@true.cz>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-08-21 17:09:13 -04:00
Russell King
04e1c83806 ARM: io: add a default IO_SPACE_LIMIT definition
Add a default IO_SPACE_LIMIT definition.  Explain the chosen value and
suggest why platforms would want to make it larger.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-08-17 08:44:17 +01:00
Russell King
1ace756628 ARM: io: ecard: move ioaddr() inside __ecard_address
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-08-17 08:44:16 +01:00
Srinivas Kandagatla
43c734be55 ARM: 7014/1: cache-l2x0: Fix L2 Cache size calculation.
This patch fixes L2 Cache size calculations for L2C-210, L2C-310 and
PL310, by changing the L2X0_AUX_CTRL_WAY_SIZE_MASK from 2 bits to 3
bits.

The Auxiliary Control Register for L2C-210, L2C-310 and PL310 has 3bits
[19:17] for Way size, however the existing code only uses 2 bits to
get this value. This results in incorrect cachesize calculations.

It also results in performing operations on the whole cache when we
erroneously decide that the range is big enough (due to l2x0_size being
too small) and also prints incorrect cachesize.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Cc: stable@kernel.org
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-08-15 11:58:59 +01:00
Nicolas Pitre
daece59689 ARM: 7013/1: P2V: Remove ARM_PATCH_PHYS_VIRT_16BIT
This code can be removed now that MSM targets no longer need the 16-bit
offsets for P2V.

Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-08-13 11:26:40 +01:00
Mark Rutland
7fdd3c4962 ARM: perf: make name of arm_pmu_type consistent
Commit f12482c9 ("ARM: 6974/1: pmu: refactor reservation") changed
{release,reserve}_pmu to take an enum arm_pmu_type as a parameter, but
inconsistently named the parameter `type' or `device'. It would be nice
if these were consistent.

This patch makes use of enum arm_pmu_type consistent, always using
`type'. Related printks are updated, explicitly mentioning `type' also.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2011-08-12 15:40:21 +01:00
Mark Rutland
49bef8331a ARM: perf: fix prototype of release_pmu
Commit  f12482c9 ("ARM: 6974/1: pmu: refactor reservation") changed the
prototype of release_pmu, but missed the stub for when
CONFIG_CPU_HAS_PMU is not selected by the platform.

This patch changes the prototype of the stub, preventing possible build
failures when CONFIG_CPU_HAS_PMU is not selected.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2011-08-12 15:40:21 +01:00
Russell King
8f3c4537bb ARM: gpio: make trivial GPIOLIB implementation the default
Rather than marking the mach/gpio.h header files which want to use the
trivial GPIOLIB implementation, mark those which do not want to use it
instead.  This means that by default, you get the trivial implementation
and only have to do something extra if you need to.  This should
encourage the use of the trivial default implementation.

As an additional bonus, several gpio.h header files become empty.

Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Tested-by: Jamie Iles <jamie@jamieiles.com>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-08-12 08:54:19 +01:00
Russell King
01e7dc89d0 ARM: gpio: consolidate gpio_to_irq
Many of the gpio_to_irq implementations use the gpiolib version of this
function.  Provide the standard gpiolib gpio_to_irq() for everyone, but
allow platforms to override it if they wish.  Add the neccessary
overrides for those platforms which do not use the standard definition.

Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-08-12 08:54:05 +01:00
Russell King
22fe678376 ARM: gpio: consolidate trivial gpiolib implementations
Consolidate 24 trivial gpiolib implementions out of mach/gpio.h
into asm/gpio.h.  This is basically the include of asm-generic/gpio.h
and the definition of gpio_get_value, gpio_set_value, and gpio_cansleep
as described in Documentation/gpio.txt

Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Tested-by: David Brown <davidb@codeaurora.org>
Acked-by: David Brown <davidb@codeaurora.org>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-08-12 08:53:15 +01:00