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0003450964
Errata i202 (OMAP3430 - 1.12, OMAP3630 - 1.6): UART module MDR1 register access can cause a dummy underrun condition which could result in a freeze in the case of IrDA communication or if used as UART, corrupted data. Workaround is as follows for everytime MDR1 register is changed: * setup all required UART registers * setup MDR1.MODE_SELECT bit field * Wait 5 L4 clk cycles + 5 UART functional clock cycles * Clear the Tx and RX fifo using FCR register Note: The following step is not done as I am assuming it is not needed due to reconfiguration being done and there is no halted operation perse. * Read if required, the RESUME register to resume halted operation Based on an earlier patch at: http://git.omapzoom.org/?p=kernel/omap.git;a=commitdiff;h=42d4a342c009bd9727c100abc8a4bc3063c22f0c Signed-off-by: Deepak K <deepak.k@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> |
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