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b2ba34f370
In the device tree for Ebony, the 'ranges' property in the node for the EBC bridge shows the mappings from the chip select / address lines actually used for the EBC peripherals into the address space of the OPB. At present, these mappings are hardcoded in ebony.dts for the mappings set up by the OpenBIOS firmware when it configures the EBC bridge. This replaces the hardcoded mappings with code in the zImage to read the EBC configuration registers and create an appropriate ranges property based on them. This should make the zImage and kernel more robust to changes in firmware configuration. In particular, some of the Ebony's DIP switches can change the effective address of the Flash and other peripherals in OPB space. With this patch, the kernel will be able to cope with at least some of the possible variations. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
86 lines
2.0 KiB
C
86 lines
2.0 KiB
C
/*
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* Copyright 2007 David Gibson, IBM Corporation.
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*
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* Based on earlier code:
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* Matt Porter <mporter@kernel.crashing.org>
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* Copyright 2002-2005 MontaVista Software Inc.
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*
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* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
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* Copyright (c) 2003, 2004 Zultys Technologies
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <stddef.h>
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#include "types.h"
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#include "string.h"
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#include "stdio.h"
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#include "ops.h"
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#include "reg.h"
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#include "dcr.h"
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/* Read the 44x memory controller to get size of system memory. */
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void ibm44x_fixup_memsize(void)
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{
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int i;
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unsigned long memsize, bank_config;
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memsize = 0;
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for (i = 0; i < ARRAY_SIZE(sdram_bxcr); i++) {
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mtdcr(DCRN_SDRAM0_CFGADDR, sdram_bxcr[i]);
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bank_config = mfdcr(DCRN_SDRAM0_CFGDATA);
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if (bank_config & SDRAM_CONFIG_BANK_ENABLE)
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memsize += SDRAM_CONFIG_BANK_SIZE(bank_config);
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}
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dt_fixup_memory(0, memsize);
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}
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#define SPRN_DBCR0 0x134
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#define DBCR0_RST_SYSTEM 0x30000000
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void ibm44x_dbcr_reset(void)
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{
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unsigned long tmp;
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asm volatile (
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"mfspr %0,%1\n"
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"oris %0,%0,%2@h\n"
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"mtspr %1,%0"
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: "=&r"(tmp) : "i"(SPRN_DBCR0), "i"(DBCR0_RST_SYSTEM)
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);
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}
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/* Read 4xx EBC bus bridge registers to get mappings of the peripheral
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* banks into the OPB address space */
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void ibm4xx_fixup_ebc_ranges(const char *ebc)
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{
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void *devp;
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u32 bxcr;
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u32 ranges[EBC_NUM_BANKS*4];
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u32 *p = ranges;
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int i;
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for (i = 0; i < EBC_NUM_BANKS; i++) {
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mtdcr(DCRN_EBC0_CFGADDR, EBC_BXCR(i));
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bxcr = mfdcr(DCRN_EBC0_CFGDATA);
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if ((bxcr & EBC_BXCR_BU) != EBC_BXCR_BU_OFF) {
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*p++ = i;
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*p++ = 0;
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*p++ = bxcr & EBC_BXCR_BAS;
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*p++ = EBC_BXCR_BANK_SIZE(bxcr);
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}
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}
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devp = finddevice(ebc);
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if (! devp)
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fatal("Couldn't locate EBC node %s\n\r", ebc);
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setprop(devp, "ranges", ranges, (p - ranges) * sizeof(u32));
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}
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