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1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
249 lines
9.2 KiB
C
249 lines
9.2 KiB
C
/* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $
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* linux/include/asm/dma.h: Defines for using and allocating dma channels.
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* Written by Hennus Bergman, 1992.
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* High DMA channel support & info by Hannu Savolainen
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* and John Boyd, Nov. 1992.
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*/
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#ifndef _ASM_APOLLO_DMA_H
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#define _ASM_APOLLO_DMA_H
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#include <asm/apollohw.h> /* need byte IO */
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#include <linux/spinlock.h> /* And spinlocks */
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#include <linux/delay.h>
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#define dma_outb(val,addr) (*((volatile unsigned char *)(addr+IO_BASE)) = (val))
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#define dma_inb(addr) (*((volatile unsigned char *)(addr+IO_BASE)))
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/*
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* NOTES about DMA transfers:
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*
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* controller 1: channels 0-3, byte operations, ports 00-1F
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* controller 2: channels 4-7, word operations, ports C0-DF
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*
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* - ALL registers are 8 bits only, regardless of transfer size
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* - channel 4 is not used - cascades 1 into 2.
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* - channels 0-3 are byte - addresses/counts are for physical bytes
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* - channels 5-7 are word - addresses/counts are for physical words
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* - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
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* - transfer count loaded to registers is 1 less than actual count
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* - controller 2 offsets are all even (2x offsets for controller 1)
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* - page registers for 5-7 don't use data bit 0, represent 128K pages
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* - page registers for 0-3 use bit 0, represent 64K pages
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*
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* DMA transfers are limited to the lower 16MB of _physical_ memory.
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* Note that addresses loaded into registers must be _physical_ addresses,
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* not logical addresses (which may differ if paging is active).
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*
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* Address mapping for channels 0-3:
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*
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* A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
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* | ... | | ... | | ... |
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* | ... | | ... | | ... |
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* | ... | | ... | | ... |
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* P7 ... P0 A7 ... A0 A7 ... A0
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* | Page | Addr MSB | Addr LSB | (DMA registers)
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*
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* Address mapping for channels 5-7:
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*
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* A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
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* | ... | \ \ ... \ \ \ ... \ \
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* | ... | \ \ ... \ \ \ ... \ (not used)
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* | ... | \ \ ... \ \ \ ... \
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* P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
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* | Page | Addr MSB | Addr LSB | (DMA registers)
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*
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* Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
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* and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
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* the hardware level, so odd-byte transfers aren't possible).
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*
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* Transfer count (_not # bytes_) is limited to 64K, represented as actual
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* count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
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* and up to 128K bytes may be transferred on channels 5-7 in one operation.
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*
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*/
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#define MAX_DMA_CHANNELS 8
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/* The maximum address that we can perform a DMA transfer to on this platform */#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x1000000)
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/* 8237 DMA controllers */
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#define IO_DMA1_BASE 0x10C00 /* 8 bit slave DMA, channels 0..3 */
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#define IO_DMA2_BASE 0x10D00 /* 16 bit master DMA, ch 4(=slave input)..7 */
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/* DMA controller registers */
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#define DMA1_CMD_REG (IO_DMA1_BASE+0x08) /* command register (w) */
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#define DMA1_STAT_REG (IO_DMA1_BASE+0x08) /* status register (r) */
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#define DMA1_REQ_REG (IO_DMA1_BASE+0x09) /* request register (w) */
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#define DMA1_MASK_REG (IO_DMA1_BASE+0x0A) /* single-channel mask (w) */
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#define DMA1_MODE_REG (IO_DMA1_BASE+0x0B) /* mode register (w) */
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#define DMA1_CLEAR_FF_REG (IO_DMA1_BASE+0x0C) /* clear pointer flip-flop (w) */
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#define DMA1_TEMP_REG (IO_DMA1_BASE+0x0D) /* Temporary Register (r) */
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#define DMA1_RESET_REG (IO_DMA1_BASE+0x0D) /* Master Clear (w) */
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#define DMA1_CLR_MASK_REG (IO_DMA1_BASE+0x0E) /* Clear Mask */
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#define DMA1_MASK_ALL_REG (IO_DMA1_BASE+0x0F) /* all-channels mask (w) */
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#define DMA2_CMD_REG (IO_DMA2_BASE+0x10) /* command register (w) */
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#define DMA2_STAT_REG (IO_DMA2_BASE+0x10) /* status register (r) */
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#define DMA2_REQ_REG (IO_DMA2_BASE+0x12) /* request register (w) */
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#define DMA2_MASK_REG (IO_DMA2_BASE+0x14) /* single-channel mask (w) */
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#define DMA2_MODE_REG (IO_DMA2_BASE+0x16) /* mode register (w) */
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#define DMA2_CLEAR_FF_REG (IO_DMA2_BASE+0x18) /* clear pointer flip-flop (w) */
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#define DMA2_TEMP_REG (IO_DMA2_BASE+0x1A) /* Temporary Register (r) */
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#define DMA2_RESET_REG (IO_DMA2_BASE+0x1A) /* Master Clear (w) */
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#define DMA2_CLR_MASK_REG (IO_DMA2_BASE+0x1C) /* Clear Mask */
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#define DMA2_MASK_ALL_REG (IO_DMA2_BASE+0x1E) /* all-channels mask (w) */
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#define DMA_ADDR_0 (IO_DMA1_BASE+0x00) /* DMA address registers */
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#define DMA_ADDR_1 (IO_DMA1_BASE+0x02)
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#define DMA_ADDR_2 (IO_DMA1_BASE+0x04)
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#define DMA_ADDR_3 (IO_DMA1_BASE+0x06)
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#define DMA_ADDR_4 (IO_DMA2_BASE+0x00)
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#define DMA_ADDR_5 (IO_DMA2_BASE+0x04)
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#define DMA_ADDR_6 (IO_DMA2_BASE+0x08)
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#define DMA_ADDR_7 (IO_DMA2_BASE+0x0C)
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#define DMA_CNT_0 (IO_DMA1_BASE+0x01) /* DMA count registers */
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#define DMA_CNT_1 (IO_DMA1_BASE+0x03)
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#define DMA_CNT_2 (IO_DMA1_BASE+0x05)
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#define DMA_CNT_3 (IO_DMA1_BASE+0x07)
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#define DMA_CNT_4 (IO_DMA2_BASE+0x02)
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#define DMA_CNT_5 (IO_DMA2_BASE+0x06)
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#define DMA_CNT_6 (IO_DMA2_BASE+0x0A)
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#define DMA_CNT_7 (IO_DMA2_BASE+0x0E)
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#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
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#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
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#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
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#define DMA_AUTOINIT 0x10
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#define DMA_8BIT 0
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#define DMA_16BIT 1
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#define DMA_BUSMASTER 2
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extern spinlock_t dma_spin_lock;
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static __inline__ unsigned long claim_dma_lock(void)
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{
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unsigned long flags;
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spin_lock_irqsave(&dma_spin_lock, flags);
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return flags;
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}
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static __inline__ void release_dma_lock(unsigned long flags)
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{
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spin_unlock_irqrestore(&dma_spin_lock, flags);
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}
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/* enable/disable a specific DMA channel */
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static __inline__ void enable_dma(unsigned int dmanr)
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{
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if (dmanr<=3)
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dma_outb(dmanr, DMA1_MASK_REG);
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else
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dma_outb(dmanr & 3, DMA2_MASK_REG);
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}
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static __inline__ void disable_dma(unsigned int dmanr)
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{
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if (dmanr<=3)
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dma_outb(dmanr | 4, DMA1_MASK_REG);
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else
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dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
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}
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/* Clear the 'DMA Pointer Flip Flop'.
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* Write 0 for LSB/MSB, 1 for MSB/LSB access.
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* Use this once to initialize the FF to a known state.
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* After that, keep track of it. :-)
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* --- In order to do that, the DMA routines below should ---
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* --- only be used while holding the DMA lock ! ---
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*/
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static __inline__ void clear_dma_ff(unsigned int dmanr)
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{
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if (dmanr<=3)
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dma_outb(0, DMA1_CLEAR_FF_REG);
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else
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dma_outb(0, DMA2_CLEAR_FF_REG);
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}
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/* set mode (above) for a specific DMA channel */
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static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
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{
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if (dmanr<=3)
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dma_outb(mode | dmanr, DMA1_MODE_REG);
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else
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dma_outb(mode | (dmanr&3), DMA2_MODE_REG);
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}
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/* Set transfer address & page bits for specific DMA channel.
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* Assumes dma flipflop is clear.
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*/
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static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
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{
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if (dmanr <= 3) {
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dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
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dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
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} else {
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dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
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dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
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}
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}
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/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
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* a specific DMA channel.
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* You must ensure the parameters are valid.
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* NOTE: from a manual: "the number of transfers is one more
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* than the initial word count"! This is taken into account.
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* Assumes dma flip-flop is clear.
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* NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
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*/
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static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
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{
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count--;
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if (dmanr <= 3) {
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dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
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dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
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} else {
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dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
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dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
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}
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}
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/* Get DMA residue count. After a DMA transfer, this
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* should return zero. Reading this while a DMA transfer is
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* still in progress will return unpredictable results.
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* If called before the channel has been used, it may return 1.
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* Otherwise, it returns the number of _bytes_ left to transfer.
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*
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* Assumes DMA flip-flop is clear.
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*/
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static __inline__ int get_dma_residue(unsigned int dmanr)
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{
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unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
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: ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
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/* using short to get 16-bit wrap around */
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unsigned short count;
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count = 1 + dma_inb(io_port);
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count += dma_inb(io_port) << 8;
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return (dmanr<=3)? count : (count<<1);
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}
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/* These are in kernel/dma.c: */
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extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
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extern void free_dma(unsigned int dmanr); /* release it again */
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/* These are in arch/m68k/apollo/dma.c: */
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extern unsigned short dma_map_page(unsigned long phys_addr,int count,int type);
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extern void dma_unmap_page(unsigned short dma_addr);
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#endif /* _ASM_APOLLO_DMA_H */
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