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bf0f2e2383
The current value was correct before the introduction of Intel EM64T support -
but now L1_CACHE_SHIFT_MAX can be less than L1_CACHE_SHIFT, which _is_ funny!
Between the few users of ____cacheline_maxaligned_in_smp, we also have (for
example) rcu_ctrlblk, and struct zone, with zone->{lru_,}lock. I.e. we have
a lot of excess cacheline bouncing on them.
No correctness issues, obviously. So this could even be merged for 2.6.14
(I'm not a fan of this idea, though).
CC: Andi Kleen <ak@suse.de>
Signed-off-by: Paolo 'Blaisorblade' Giarrusso <blaisorblade@yahoo.it>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
15 lines
322 B
C
15 lines
322 B
C
/*
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* include/asm-x8664/cache.h
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*/
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#ifndef __ARCH_X8664_CACHE_H
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#define __ARCH_X8664_CACHE_H
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#include <linux/config.h>
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/* L1 cache line size */
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#define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT)
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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#define L1_CACHE_SHIFT_MAX 7 /* largest L1 which this arch supports */
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#endif
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