Jason Gunthorpe 425902f5c8 fpga zynq: Use the scatterlist interface ...

This allows the driver to avoid a high order coherent DMA allocation
and memory copy. With this patch it can DMA directly from the kernel
pages that the bitfile is stored in.

Since this is now a gather DMA operation the driver uses the ISR
to feed the chips DMA queue with each entry from the SGL.

Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Acked-by: Moritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

2017-02-10 15:20:44 +01:00

..

altera-fpga2sdram.c

ARM: socfpga: checking the wrong variable

2016-11-17 08:14:55 +01:00

altera-freeze-bridge.c

fpga: add altera freeze bridge support

2016-11-10 17:03:36 +01:00

altera-hps2fpga.c

ARM: socfpga: fpga bridge driver support

2016-11-10 17:03:36 +01:00

fpga-bridge.c

fpga: add fpga bridge framework

2016-11-10 17:03:35 +01:00

fpga-mgr.c

fpga: Add scatterlist based programming

2017-02-10 15:20:44 +01:00

fpga-region.c

fpga: fpga-region: device tree control for FPGA

2016-11-10 17:03:35 +01:00

Kconfig

fpga: Add COMPILE_TEST to all drivers

2016-11-29 15:51:44 -06:00

Makefile

fpga-manager: Add Socfpga Arria10 support

2016-11-10 17:03:36 +01:00

socfpga-a10.c

fpga: Clarify how write_init works streaming modes

2016-11-29 15:51:49 -06:00

socfpga.c

…

zynq-fpga.c

fpga zynq: Use the scatterlist interface

2017-02-10 15:20:44 +01:00