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375074cc73
CR4 manipulation was split, seemingly at random, between direct (write_cr4) and using a helper (set/clear_in_cr4). Unfortunately, the set_in_cr4 and clear_in_cr4 helpers also poke at the boot code, which only a small subset of users actually wanted. This patch replaces all cr4 access in functions that don't leave cr4 exactly the way they found it with new helpers cr4_set_bits, cr4_clear_bits, and cr4_set_bits_and_update_boot. Signed-off-by: Andy Lutomirski <luto@amacapital.net> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Andrea Arcangeli <aarcange@redhat.com> Cc: Vince Weaver <vince@deater.net> Cc: "hillf.zj" <hillf.zj@alibaba-inc.com> Cc: Valdis Kletnieks <Valdis.Kletnieks@vt.edu> Cc: Paul Mackerras <paulus@samba.org> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Kees Cook <keescook@chromium.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Link: http://lkml.kernel.org/r/495a10bdc9e67016b8fd3945700d46cfd5c12c2f.1414190806.git.luto@amacapital.net Signed-off-by: Ingo Molnar <mingo@kernel.org>
74 lines
1.8 KiB
C
74 lines
1.8 KiB
C
/*
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* P5 specific Machine Check Exception Reporting
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* (C) Copyright 2002 Alan Cox <alan@lxorguk.ukuu.org.uk>
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*/
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/smp.h>
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#include <asm/processor.h>
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#include <asm/traps.h>
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#include <asm/tlbflush.h>
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#include <asm/mce.h>
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#include <asm/msr.h>
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/* By default disabled */
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int mce_p5_enabled __read_mostly;
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/* Machine check handler for Pentium class Intel CPUs: */
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static void pentium_machine_check(struct pt_regs *regs, long error_code)
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{
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enum ctx_state prev_state;
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u32 loaddr, hi, lotype;
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prev_state = ist_enter(regs);
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rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi);
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rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi);
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printk(KERN_EMERG
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"CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n",
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smp_processor_id(), loaddr, lotype);
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if (lotype & (1<<5)) {
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printk(KERN_EMERG
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"CPU#%d: Possible thermal failure (CPU on fire ?).\n",
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smp_processor_id());
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}
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add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
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ist_exit(regs, prev_state);
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}
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/* Set up machine check reporting for processors with Intel style MCE: */
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void intel_p5_mcheck_init(struct cpuinfo_x86 *c)
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{
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u32 l, h;
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/* Default P5 to off as its often misconnected: */
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if (!mce_p5_enabled)
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return;
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/* Check for MCE support: */
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if (!cpu_has(c, X86_FEATURE_MCE))
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return;
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machine_check_vector = pentium_machine_check;
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/* Make sure the vector pointer is visible before we enable MCEs: */
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wmb();
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/* Read registers before enabling: */
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rdmsr(MSR_IA32_P5_MC_ADDR, l, h);
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rdmsr(MSR_IA32_P5_MC_TYPE, l, h);
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printk(KERN_INFO
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"Intel old style machine check architecture supported.\n");
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/* Enable MCE: */
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cr4_set_bits(X86_CR4_MCE);
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printk(KERN_INFO
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"Intel old style machine check reporting enabled on CPU#%d.\n",
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smp_processor_id());
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}
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