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a4b5bd9abc
Expand SB1 cache error handling by adding SB1_CEX_ALWAYS_FATAL and
SB1_CEX_STALL, allowing configurable behavior on cache errors.
Signed-Off-By: Andy Isaacson <adi@broadcom.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
162 lines
3.4 KiB
Plaintext
162 lines
3.4 KiB
Plaintext
config SIBYTE_SB1250
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bool
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select HW_HAS_PCI
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select SIBYTE_HAS_LDT
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select SIBYTE_SB1xxx_SOC
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config SIBYTE_BCM1120
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bool
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select SIBYTE_BCM112X
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select SIBYTE_SB1xxx_SOC
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config SIBYTE_BCM1125
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bool
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select HW_HAS_PCI
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select SIBYTE_BCM112X
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select SIBYTE_SB1xxx_SOC
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config SIBYTE_BCM1125H
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bool
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select HW_HAS_PCI
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select SIBYTE_BCM112X
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select SIBYTE_HAS_LDT
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select SIBYTE_SB1xxx_SOC
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config SIBYTE_BCM112X
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bool
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select SIBYTE_SB1xxx_SOC
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config SIBYTE_BCM1x80
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bool
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select HW_HAS_PCI
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select SIBYTE_SB1xxx_SOC
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config SIBYTE_BCM1x55
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bool
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select HW_HAS_PCI
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select SIBYTE_SB1xxx_SOC
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config SIBYTE_SB1xxx_SOC
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bool
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depends on EXPERIMENTAL
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select DMA_COHERENT
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select SIBYTE_CFE
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select SWAP_IO_SPACE
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_64BIT_KERNEL
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choice
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prompt "SiByte SOC Stepping"
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depends on SIBYTE_SB1xxx_SOC
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config CPU_SB1_PASS_1
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bool "1250 Pass1"
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depends on SIBYTE_SB1250
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select CPU_HAS_PREFETCH
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config CPU_SB1_PASS_2_1250
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bool "1250 An"
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depends on SIBYTE_SB1250
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select CPU_SB1_PASS_2
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help
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Also called BCM1250 Pass 2
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config CPU_SB1_PASS_2_2
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bool "1250 Bn"
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depends on SIBYTE_SB1250
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select CPU_HAS_PREFETCH
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help
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Also called BCM1250 Pass 2.2
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config CPU_SB1_PASS_4
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bool "1250 Cn"
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depends on SIBYTE_SB1250
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select CPU_HAS_PREFETCH
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help
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Also called BCM1250 Pass 3
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config CPU_SB1_PASS_2_112x
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bool "112x Hybrid"
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depends on SIBYTE_BCM112X
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select CPU_SB1_PASS_2
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config CPU_SB1_PASS_3
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bool "112x An"
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depends on SIBYTE_BCM112X
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select CPU_HAS_PREFETCH
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endchoice
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config CPU_SB1_PASS_2
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bool
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config SIBYTE_HAS_LDT
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bool
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depends on PCI && (SIBYTE_SB1250 || SIBYTE_BCM1125H)
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default y
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config SIMULATION
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bool "Running under simulation"
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depends on SIBYTE_SB1xxx_SOC
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help
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Build a kernel suitable for running under the GDB simulator.
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Primarily adjusts the kernel's notion of time.
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config CONFIG_SB1_CEX_ALWAYS_FATAL
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bool "All cache exceptions considered fatal (no recovery attempted)"
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depends on SIBYTE_SB1xxx_SOC
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config CONFIG_SB1_CERR_STALL
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bool "Stall (rather than panic) on fatal cache error"
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depends on SIBYTE_SB1xxx_SOC
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config SIBYTE_CFE
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bool "Booting from CFE"
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depends on SIBYTE_SB1xxx_SOC
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help
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Make use of the CFE API for enumerating available memory,
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controlling secondary CPUs, and possibly console output.
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config SIBYTE_CFE_CONSOLE
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bool "Use firmware console"
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depends on SIBYTE_CFE
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help
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Use the CFE API's console write routines during boot. Other console
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options (VT console, sb1250 duart console, etc.) should not be
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configured.
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config SIBYTE_STANDALONE
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bool
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depends on SIBYTE_SB1xxx_SOC && !SIBYTE_CFE
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default y
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config SIBYTE_STANDALONE_RAM_SIZE
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int "Memory size (in megabytes)"
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depends on SIBYTE_STANDALONE
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default "32"
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config SIBYTE_BUS_WATCHER
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bool "Support for Bus Watcher statistics"
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depends on SIBYTE_SB1xxx_SOC
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help
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Handle and keep statistics on the bus error interrupts (COR_ECC,
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BAD_ECC, IO_BUS).
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config SIBYTE_BW_TRACE
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bool "Capture bus trace before bus error"
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depends on SIBYTE_BUS_WATCHER
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help
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Run a continuous bus trace, dumping the raw data as soon as
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a ZBbus error is detected. Cannot work if ZBbus profiling
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is turned on, and also will interfere with JTAG-based trace
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buffer activity. Raw buffer data is dumped to console, and
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must be processed off-line.
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config SIBYTE_SB1250_PROF
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bool "Support for SB1/SOC profiling - SB1/SCD perf counters"
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depends on SIBYTE_SB1xxx_SOC
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config SIBYTE_TBPROF
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bool "Support for ZBbus profiling"
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depends on SIBYTE_SB1xxx_SOC
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