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0d4ae36062
- Add support for the Clock Pulse Generator / Module Standby and Software Reset module on revision ES2.0 of the R-Car H3 SoC, which differs from ES1.x in some areas. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJY3h3eAAoJEEgEtLw/Ve77F5MP/REcR7bb9TmdCDwXFpMXmZtw jigpASslArlBsBfWsGX3oalkrrKLY+qs8d8++9+OIYdvf6stFNEH5E0PoOTOmNGY bs6NnXNXxKoRIe/HK2bXYav2MAmf2fDNWFSnWapygV9j8CjudCEPrK+GZcWI+0ED Sy5zE/exnPb/oZp5VutzZNiCAuI79iXjtIDOZDidQxwzC/AOQ2wq99ieclEafABX F5XQkUtYjEzu7DgX2Luy0f7GMlNCVlaYbM1oi41Reka9UF8Ei3G7tLX+/qNgkyu3 U6HMRbiQBkOKVBAfKetmOyAJxhHk1R+Q6e9Qm3LJqHVt9Ar9nclybEcRMcYMJFpB aF9mehg0U/3yyX3IW7arXTCLegSPsOLn+Hgo1b8tG2BZKsMQrd86elVVGPODkDZj CQyge358wvMKzqTozGjP9s8TetU0lpQI7HrK0/X0dNmYnJlejJ0mi3cSUu+Rp8al +tbMJL47W3JxBFhh1kBJGMoUW3glbDYdlwyvGy/Fsl84TCWD6bmKh8AhRQrYbOR8 Jo3CiH22HPHAT0TWXwOhEuB6TxDacpA7Wf0dDN0EPRZ2kGrRvjvxv7zg8BPKCGcA G6uTX+Wlov8TTwYzluLtfbbRS0Kmcx0ZcuKAmgoV9991e4IC6YKaBok4ArqfEdwR BcnSkpRriiVRqbj17Hdi =rttL -----END PGP SIGNATURE----- Merge tag 'clk-renesas-for-v4.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull Renesas clk driver updates from Geert Uytterhoeven: - Add support for the Clock Pulse Generator / Module Standby and Software Reset module on revision ES2.0 of the R-Car H3 SoC, which differs from ES1.x in some areas. - Add IMR clocks for R-Car H3 and M3-W, - Add workaround for PLL0/2/4 errata on R-Car H3 ES1.0, - Small fixes and cleanups. * tag 'clk-renesas-for-v4.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: rcar-gen3-cpg: Add support for RCLK on R-Car H3 ES2.0 clk: renesas: r8a7795: Add support for R-Car H3 ES2.0 clk: renesas: Add r8a7795 ES2.0 CPG Core Clock Definitions clk: renesas: cpg-mssr: Add support for fixing up clock tables clk: renesas: rcar-gen3: Add workaround for PLL0/2/4 errata on H3 ES1.0 clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init() clk: renesas: r8a7796: Reformat core clock table clk: renesas: r8a7795: Reformat core clock table clk: renesas: r8a7796: Correct name of watchdog clock clk: renesas: r8a7795: Correct name of watchdog clock clk: renesas: r8a7795: Correct parent clock and sort order for Audio DMACs clk: renesas: r8a7796: Add IMR clocks clk: renesas: r8a7795: Add IMR clocks |
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