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4a66b5d980
Without this exiting WFI can result in cache corruption. Code taken from Freescale's 2.6.27 BSP and tested on i.MX35 Signed-off-by: Eric Bénard <eric@eukrea.com>
64 lines
1.8 KiB
C
64 lines
1.8 KiB
C
/*
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* Copyright (C) 1999 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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* Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __ASM_ARCH_MXC_SYSTEM_H__
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#define __ASM_ARCH_MXC_SYSTEM_H__
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#include <mach/hardware.h>
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#include <mach/common.h>
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static inline void arch_idle(void)
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{
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#ifdef CONFIG_ARCH_MXC91231
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if (cpu_is_mxc91231()) {
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/* Need this to set DSM low-power mode */
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mxc91231_prepare_idle();
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}
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#endif
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/* fix i.MX31 errata TLSbo65953 and i.MX35 errata ENGcm09472 */
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if (cpu_is_mx31() || cpu_is_mx35()) {
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unsigned long reg = 0;
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__asm__ __volatile__(
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/* disable I and D cache */
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"mrc p15, 0, %0, c1, c0, 0\n"
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"bic %0, %0, #0x00001000\n"
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"bic %0, %0, #0x00000004\n"
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"mcr p15, 0, %0, c1, c0, 0\n"
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/* invalidate I cache */
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"mov %0, #0\n"
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"mcr p15, 0, %0, c7, c5, 0\n"
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/* clear and invalidate D cache */
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"mov %0, #0\n"
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"mcr p15, 0, %0, c7, c14, 0\n"
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/* WFI */
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"mov %0, #0\n"
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"mcr p15, 0, %0, c7, c0, 4\n"
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"nop\n" "nop\n" "nop\n" "nop\n"
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"nop\n" "nop\n" "nop\n"
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/* enable I and D cache */
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"mrc p15, 0, %0, c1, c0, 0\n"
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"orr %0, %0, #0x00001000\n"
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"orr %0, %0, #0x00000004\n"
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"mcr p15, 0, %0, c1, c0, 0\n"
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: "=r" (reg));
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} else
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cpu_do_idle();
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}
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void arch_reset(char mode, const char *cmd);
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#endif /* __ASM_ARCH_MXC_SYSTEM_H__ */
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