Peter Ujfalusi
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ASoC: tas2552: Correct the PLL configuration ...
Do not restrict the sampling rate to 44.1/48KHz. The pll_clk clock should
be (sampling rate * 512) in all cases.
Correct the J.D calculation (the D part was incorrectly calculated).
Restore PLL enable status after we are done with the configuration.
Implement hardware constraint handling towards the pll_clkin:
if D != 0 (in J.D) then 1.1MHz <= pll_clkin <= 9.2MHz needs to be checked.
If the PLL setup does not met with this constraint, fall back to BCLK as
reference clock, if BCLK fails, use the internal 1.8MHz clock.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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