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4162d7e363
GPIO register and configuration definitions for GPIO banks G, H, I and J. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
43 lines
1.4 KiB
C
43 lines
1.4 KiB
C
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* GPIO Bank G register and configuration definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#define S3C64XX_GPGCON (S3C64XX_GPG_BASE + 0x00)
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#define S3C64XX_GPGDAT (S3C64XX_GPG_BASE + 0x04)
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#define S3C64XX_GPGPUD (S3C64XX_GPG_BASE + 0x08)
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#define S3C64XX_GPGCONSLP (S3C64XX_GPG_BASE + 0x0c)
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#define S3C64XX_GPGPUDSLP (S3C64XX_GPG_BASE + 0x10)
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#define S3C64XX_GPG_CONMASK(__gpio) (0xf << ((__gpio) * 4))
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#define S3C64XX_GPG_INPUT(__gpio) (0x0 << ((__gpio) * 4))
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#define S3C64XX_GPG_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
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#define S3C64XX_GPG0_MMC0_CLK (0x02 << 0)
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#define S3C64XX_GPG0_EINT_G5_0 (0x07 << 0)
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#define S3C64XX_GPG1_MMC0_CMD (0x02 << 4)
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#define S3C64XX_GPG1_EINT_G5_1 (0x07 << 4)
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#define S3C64XX_GPG2_MMC0_DATA0 (0x02 << 8)
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#define S3C64XX_GPG2_EINT_G5_2 (0x07 << 8)
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#define S3C64XX_GPG3_MMC0_DATA1 (0x02 << 12)
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#define S3C64XX_GPG3_EINT_G5_3 (0x07 << 12)
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#define S3C64XX_GPG4_MMC0_DATA2 (0x02 << 16)
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#define S3C64XX_GPG4_EINT_G5_4 (0x07 << 16)
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#define S3C64XX_GPG5_MMC0_DATA3 (0x02 << 20)
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#define S3C64XX_GPG5_EINT_G5_5 (0x07 << 20)
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