mirror of
https://github.com/FEX-Emu/linux.git
synced 2024-12-25 10:59:05 +00:00
41907ddc1b
When I refactored the code initially, I forgot that gen2 uses a
different bar for the CPU mappable aperture. The agp-less code knows
nothing of generations less than 5, so we have to expand the gtt_probe
function to include the mappable base and end.
It was originally broken by me:
commit baa09f5fd8
Author: Ben Widawsky <ben@bwidawsk.net>
Date: Thu Jan 24 13:49:57 2013 -0800
drm/i915: Add probe and remove to the gtt ops
Reported-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
33 lines
860 B
C
33 lines
860 B
C
/* Common header for intel-gtt.ko and i915.ko */
|
|
|
|
#ifndef _DRM_INTEL_GTT_H
|
|
#define _DRM_INTEL_GTT_H
|
|
|
|
void intel_gtt_get(size_t *gtt_total, size_t *stolen_size,
|
|
phys_addr_t *mappable_base, unsigned long *mappable_end);
|
|
|
|
int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
|
|
struct agp_bridge_data *bridge);
|
|
void intel_gmch_remove(void);
|
|
|
|
bool intel_enable_gtt(void);
|
|
|
|
void intel_gtt_chipset_flush(void);
|
|
void intel_gtt_insert_sg_entries(struct sg_table *st,
|
|
unsigned int pg_start,
|
|
unsigned int flags);
|
|
void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries);
|
|
|
|
/* Special gtt memory types */
|
|
#define AGP_DCACHE_MEMORY 1
|
|
#define AGP_PHYS_MEMORY 2
|
|
|
|
/* flag for GFDT type */
|
|
#define AGP_USER_CACHED_MEMORY_GFDT (1 << 3)
|
|
|
|
#ifdef CONFIG_INTEL_IOMMU
|
|
extern int intel_iommu_gfx_mapped;
|
|
#endif
|
|
|
|
#endif
|