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1965aae3c9
Change header guards named "ASM_X86__*" to "_ASM_X86_*" since: a. the double underscore is ugly and pointless. b. no leading underscore violates namespace constraints. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
157 lines
3.8 KiB
C
157 lines
3.8 KiB
C
#ifndef _ASM_X86_MACH_DEFAULT__MACH_APIC_H
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#define _ASM_X86_MACH_DEFAULT__MACH_APIC_H
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#ifdef CONFIG_X86_LOCAL_APIC
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#include <mach_apicdef.h>
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#include <asm/smp.h>
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#define APIC_DFR_VALUE (APIC_DFR_FLAT)
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static inline cpumask_t target_cpus(void)
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{
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#ifdef CONFIG_SMP
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return cpu_online_map;
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#else
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return cpumask_of_cpu(0);
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#endif
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}
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#define NO_BALANCE_IRQ (0)
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#define esr_disable (0)
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#ifdef CONFIG_X86_64
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#include <asm/genapic.h>
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#define INT_DELIVERY_MODE (genapic->int_delivery_mode)
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#define INT_DEST_MODE (genapic->int_dest_mode)
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#define TARGET_CPUS (genapic->target_cpus())
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#define apic_id_registered (genapic->apic_id_registered)
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#define init_apic_ldr (genapic->init_apic_ldr)
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#define cpu_mask_to_apicid (genapic->cpu_mask_to_apicid)
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#define phys_pkg_id (genapic->phys_pkg_id)
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#define vector_allocation_domain (genapic->vector_allocation_domain)
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#define read_apic_id() (GET_APIC_ID(apic_read(APIC_ID)))
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#define send_IPI_self (genapic->send_IPI_self)
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extern void setup_apic_routing(void);
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#else
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#define INT_DELIVERY_MODE dest_LowestPrio
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#define INT_DEST_MODE 1 /* logical delivery broadcast to all procs */
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#define TARGET_CPUS (target_cpus())
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/*
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* Set up the logical destination ID.
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*
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* Intel recommends to set DFR, LDR and TPR before enabling
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* an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
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* document number 292116). So here it goes...
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*/
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static inline void init_apic_ldr(void)
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{
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unsigned long val;
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apic_write(APIC_DFR, APIC_DFR_VALUE);
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val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
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val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
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apic_write(APIC_LDR, val);
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}
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static inline int apic_id_registered(void)
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{
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return physid_isset(read_apic_id(), phys_cpu_present_map);
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}
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static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
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{
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return cpus_addr(cpumask)[0];
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}
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static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
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{
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return cpuid_apic >> index_msb;
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}
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static inline void setup_apic_routing(void)
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{
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#ifdef CONFIG_X86_IO_APIC
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printk("Enabling APIC mode: %s. Using %d I/O APICs\n",
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"Flat", nr_ioapics);
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#endif
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}
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static inline int apicid_to_node(int logical_apicid)
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{
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#ifdef CONFIG_SMP
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return apicid_2_node[hard_smp_processor_id()];
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#else
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return 0;
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#endif
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}
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static inline cpumask_t vector_allocation_domain(int cpu)
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{
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/* Careful. Some cpus do not strictly honor the set of cpus
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* specified in the interrupt destination when using lowest
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* priority interrupt delivery mode.
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*
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* In particular there was a hyperthreading cpu observed to
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* deliver interrupts to the wrong hyperthread when only one
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* hyperthread was specified in the interrupt desitination.
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*/
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cpumask_t domain = { { [0] = APIC_ALL_CPUS, } };
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return domain;
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}
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#endif
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static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
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{
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return physid_isset(apicid, bitmap);
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}
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static inline unsigned long check_apicid_present(int bit)
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{
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return physid_isset(bit, phys_cpu_present_map);
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}
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static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
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{
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return phys_map;
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}
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static inline int multi_timer_check(int apic, int irq)
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{
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return 0;
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}
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/* Mapping from cpu number to logical apicid */
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static inline int cpu_to_logical_apicid(int cpu)
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{
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return 1 << cpu;
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}
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static inline int cpu_present_to_apicid(int mps_cpu)
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{
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if (mps_cpu < NR_CPUS && cpu_present(mps_cpu))
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return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
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else
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return BAD_APICID;
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}
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static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
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{
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return physid_mask_of_physid(phys_apicid);
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}
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static inline void setup_portio_remap(void)
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{
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}
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static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
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{
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return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map);
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}
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static inline void enable_apic_mode(void)
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{
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}
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#endif /* CONFIG_X86_LOCAL_APIC */
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#endif /* _ASM_X86_MACH_DEFAULT__MACH_APIC_H */
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