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1b29187315
The e6500 core used on T4240 and B4860 SoCs from FSL implements MMUv2 of the Power Book-E Architecture. However there are some minor differences between it and other Book-E implementations. Add support to parse SPRN_TLB1PS for the variable page sizes supported. In the future this should be expanded for more page sizes supported on e6500 as well as other MMU features. This patch is based on code from Scott Wood. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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| .. | ||
| 40x_mmu.c | ||
| 44x_mmu.c | ||
| dma-noncoherent.c | ||
| fault.c | ||
| fsl_booke_mmu.c | ||
| gup.c | ||
| hash_low_32.S | ||
| hash_low_64.S | ||
| hash_native_64.c | ||
| hash_utils_64.c | ||
| highmem.c | ||
| hugetlbpage-book3e.c | ||
| hugetlbpage-hash64.c | ||
| hugetlbpage.c | ||
| icswx_pid.c | ||
| icswx.c | ||
| icswx.h | ||
| init_32.c | ||
| init_64.c | ||
| Makefile | ||
| mem.c | ||
| mmap_64.c | ||
| mmu_context_hash32.c | ||
| mmu_context_hash64.c | ||
| mmu_context_nohash.c | ||
| mmu_decl.h | ||
| numa.c | ||
| pgtable_32.c | ||
| pgtable_64.c | ||
| pgtable.c | ||
| ppc_mmu_32.c | ||
| slb_low.S | ||
| slb.c | ||
| slice.c | ||
| stab.c | ||
| subpage-prot.c | ||
| tlb_hash32.c | ||
| tlb_hash64.c | ||
| tlb_low_64e.S | ||
| tlb_nohash_low.S | ||
| tlb_nohash.c | ||