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1c69524c2e
4 socket quad core, 8 socket quad core will do apic ID lifting for BSP. But io-apic regs for ExtINT still use 0 as dest. so when we enable apic error vector in BSP, we will get one APIC error. CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line) CPU: L2 Cache: 512K (64 bytes/line) CPU 0/4 -> Node 0 CPU: Physical Processor ID: 1 CPU: Processor Core ID: 0 SMP alternatives: switching to UP code ACPI: Core revision 20070126 enabled ExtINT on CPU#0 ESR value after enabling vector: 00000000, after 0000000c APIC error on CPU0: 0c(08) ENABLING IO-APIC IRQs Synchronizing Arb IDs. So move enable_IO_APIC from setup_IO_APIC into setup_local_APIC and call it before enabling the ACPI error vector. [ tglx: arch/x86 adaptation ] Signed-off-by: Yinghai Lu <yinghai.lu@sun.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> |
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.. | ||
boot | ||
configs | ||
crypto | ||
ia32 | ||
kernel | ||
lguest | ||
lib | ||
mach-default | ||
mach-es7000 | ||
mach-generic | ||
mach-visws | ||
mach-voyager | ||
math-emu | ||
mm | ||
oprofile | ||
pci | ||
power | ||
vdso | ||
video | ||
xen | ||
Kconfig | ||
Kconfig.cpu | ||
Kconfig.debug | ||
Makefile | ||
Makefile_32 | ||
Makefile_32.cpu | ||
Makefile_64 |