mirror of
https://github.com/FEX-Emu/linux.git
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1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
152 lines
5.2 KiB
C
152 lines
5.2 KiB
C
/*
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* pci-vr41xx.h, Include file for PCI Control Unit of the NEC VR4100 series.
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*
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* Copyright (C) 2002 MontaVista Software Inc.
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* Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
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* Copyright (C) 2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __PCI_VR41XX_H
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#define __PCI_VR41XX_H
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#define PCIMMAW1REG KSEG1ADDR(0x0f000c00)
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#define PCIMMAW2REG KSEG1ADDR(0x0f000c04)
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#define PCITAW1REG KSEG1ADDR(0x0f000c08)
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#define PCITAW2REG KSEG1ADDR(0x0f000c0c)
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#define PCIMIOAWREG KSEG1ADDR(0x0f000c10)
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#define IBA(addr) ((addr) & 0xff000000U)
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#define MASTER_MSK(mask) (((mask) >> 11) & 0x000fe000U)
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#define PCIA(addr) (((addr) >> 24) & 0x000000ffU)
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#define TARGET_MSK(mask) (((mask) >> 8) & 0x000fe000U)
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#define ITA(addr) (((addr) >> 24) & 0x000000ffU)
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#define PCIIA(addr) (((addr) >> 24) & 0x000000ffU)
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#define WINEN 0x1000U
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#define PCICONFDREG KSEG1ADDR(0x0f000c14)
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#define PCICONFAREG KSEG1ADDR(0x0f000c18)
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#define PCIMAILREG KSEG1ADDR(0x0f000c1c)
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#define BUSERRADREG KSEG1ADDR(0x0f000c24)
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#define EA(reg) ((reg) &0xfffffffc)
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#define INTCNTSTAREG KSEG1ADDR(0x0f000c28)
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#define MABTCLR 0x80000000U
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#define TRDYCLR 0x40000000U
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#define PARCLR 0x20000000U
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#define MBCLR 0x10000000U
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#define SERRCLR 0x08000000U
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#define RTYCLR 0x04000000U
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#define MABCLR 0x02000000U
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#define TABCLR 0x01000000U
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/* RFU */
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#define MABTMSK 0x00008000U
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#define TRDYMSK 0x00004000U
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#define PARMSK 0x00002000U
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#define MBMSK 0x00001000U
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#define SERRMSK 0x00000800U
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#define RTYMSK 0x00000400U
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#define MABMSK 0x00000200U
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#define TABMSK 0x00000100U
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#define IBAMABT 0x00000080U
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#define TRDYRCH 0x00000040U
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#define PAR 0x00000020U
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#define MB 0x00000010U
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#define PCISERR 0x00000008U
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#define RTYRCH 0x00000004U
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#define MABORT 0x00000002U
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#define TABORT 0x00000001U
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#define PCIEXACCREG KSEG1ADDR(0x0f000c2c)
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#define UNLOCK 0x2U
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#define EAREQ 0x1U
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#define PCIRECONTREG KSEG1ADDR(0x0f000c30)
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#define RTRYCNT(reg) ((reg) & 0x000000ffU)
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#define PCIENREG KSEG1ADDR(0x0f000c34)
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#define BLOODY_CONFIG_DONE 0x4U
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#define PCICLKSELREG KSEG1ADDR(0x0f000c38)
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#define EQUAL_VTCLOCK 0x2U
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#define HALF_VTCLOCK 0x0U
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#define ONE_THIRD_VTCLOCK 0x3U
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#define QUARTER_VTCLOCK 0x1U
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#define PCITRDYVREG KSEG1ADDR(0x0f000c3c)
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#define TRDYV(val) ((uint32_t)(val) & 0xffU)
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#define PCICLKRUNREG KSEG1ADDR(0x0f000c60)
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#define VENDORIDREG KSEG1ADDR(0x0f000d00)
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#define DEVICEIDREG KSEG1ADDR(0x0f000d00)
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#define COMMANDREG KSEG1ADDR(0x0f000d04)
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#define STATUSREG KSEG1ADDR(0x0f000d04)
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#define REVIDREG KSEG1ADDR(0x0f000d08)
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#define CLASSREG KSEG1ADDR(0x0f000d08)
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#define CACHELSREG KSEG1ADDR(0x0f000d0c)
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#define LATTIMEREG KSEG1ADDR(0x0f000d0c)
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#define MLTIM(val) (((uint32_t)(val) << 7) & 0xff00U)
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#define MAILBAREG KSEG1ADDR(0x0f000d10)
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#define PCIMBA1REG KSEG1ADDR(0x0f000d14)
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#define PCIMBA2REG KSEG1ADDR(0x0f000d18)
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#define MBADD(base) ((base) & 0xfffff800U)
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#define PMBA(base) ((base) & 0xffe00000U)
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#define PREF 0x8U
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#define PREF_APPROVAL 0x8U
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#define PREF_DISAPPROVAL 0x0U
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#define TYPE 0x6U
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#define TYPE_32BITSPACE 0x0U
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#define MSI 0x1U
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#define MSI_MEMORY 0x0U
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#define INTLINEREG KSEG1ADDR(0x0f000d3c)
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#define INTPINREG KSEG1ADDR(0x0f000d3c)
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#define RETVALREG KSEG1ADDR(0x0f000d40)
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#define PCIAPCNTREG KSEG1ADDR(0x0f000d40)
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#define TKYGNT 0x04000000U
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#define TKYGNT_ENABLE 0x04000000U
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#define TKYGNT_DISABLE 0x00000000U
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#define PAPC 0x03000000U
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#define PAPC_ALTERNATE_B 0x02000000U
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#define PAPC_ALTERNATE_0 0x01000000U
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#define PAPC_FAIR 0x00000000U
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#define RTYVAL(val) (((uint32_t)(val) << 7) & 0xff00U)
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#define RTYVAL_MASK 0xff00U
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#define PCI_CLOCK_MAX 33333333U
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/*
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* Default setup
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*/
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#define PCI_MASTER_MEM1_BUS_BASE_ADDRESS 0x10000000U
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#define PCI_MASTER_MEM1_ADDRESS_MASK 0x7c000000U
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#define PCI_MASTER_MEM1_PCI_BASE_ADDRESS 0x10000000U
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#define PCI_TARGET_MEM1_ADDRESS_MASK 0x08000000U
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#define PCI_TARGET_MEM1_BUS_BASE_ADDRESS 0x00000000U
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#define PCI_MASTER_IO_BUS_BASE_ADDRESS 0x16000000U
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#define PCI_MASTER_IO_ADDRESS_MASK 0x7e000000U
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#define PCI_MASTER_IO_PCI_BASE_ADDRESS 0x00000000U
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#define PCI_MAILBOX_BASE_ADDRESS 0x00000000U
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#define PCI_TARGET_WINDOW1_BASE_ADDRESS 0x00000000U
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#define IO_PORT_BASE KSEG1ADDR(PCI_MASTER_IO_BUS_BASE_ADDRESS)
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#define IO_PORT_RESOURCE_START PCI_MASTER_IO_PCI_BASE_ADDRESS
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#define IO_PORT_RESOURCE_END (~PCI_MASTER_IO_ADDRESS_MASK & PCI_MASTER_ADDRESS_MASK)
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#define PCI_IO_RESOURCE_START 0x01000000UL
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#define PCI_IO_RESOURCE_END 0x01ffffffUL
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#define PCI_MEM_RESOURCE_START 0x11000000UL
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#define PCI_MEM_RESOURCE_END 0x13ffffffUL
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#endif /* __PCI_VR41XX_H */
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